Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Rudnicki, R.; Kropidłowski, Marek; Handkiewicz, Andrzej

doi:10.1002/cta.576

Cited by 10 publications

(7 citation statements)

References 12 publications

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“…Thanks to such feature, the proposed FPAA concept can be used for ASIC or IPcore devices assembled with smaller modules, depending on required resources. [36] pair and 8 with SI memory cells [17] with delay elements. Let us notice that routing is a part of ROWs.…”

Section: Routing Of Arraymentioning

confidence: 99%

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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This article introduces a current-mode field-programmable analog array (FPAA) architecture with its programming methods. The biggest benefit of the proposed approach is solving the problem of implementing reconfigurable analog circuits in modern nanometre technologies. It is achieved thanks to adopting a switched-current (SI) technique which allows to implement the array using transistors based only on the standard digital CMOS technology. The work describes an implementation of a reconfigurable current mirror basing on using a digital-to-analog converter. The article addresses a routing problem of current-mode modules working in a balanced mode. Author proposes methods for CMRR compensation in a huge array architecture. The array was programmed taking into consideration parasitic elements of the layout with the emphasis on topography mismatch. Examples of implementing a 10-bit digital-analog converter, an elliptic filter with SNR = 40.42 dB, 2D-DCT processor with PSNR = 53.05 dB and RGB-to-YCrCb converter with PSNR = 46.95 dB are presented. The elaborated array can be used as IPcore in a larger mixed-signal system or can act as a dedicated circuit.

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Section: Routing Of Arraymentioning

confidence: 99%

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

SzczăźSny

2016

Circuits Syst Signal Process

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“…The selected examples of the SI-Studio application are presented in [37]. The resulting SI filter consists of bilinear switched-current integrators [38] as well as parameterized current mirrors. The matrices B x and B y are also implemented using current mirrors.…”

Section: Analog Detailed-emphasis Filtermentioning

confidence: 99%

Analogue CMOS ASICs in Image Processing Systems

Jendernalik¹,

Blakiewicz²,

Handkiewicz³

et al. 2013

Metrology and Measurement Systems

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In this paper a survey of analog application specific integrated circuits (ASICs) for low-level image processing, called vision chips, is presented. Due to the specific requirements, the vision chips are designed using different architectures best suited to their functions. The main types of the vision chip architectures and their properties are presented and characterized on selected examples of prototype integrated circuits (ICs) fabricated in complementary metal oxide semiconductor (CMOS) technologies. While discussing the vision chip realizations the importance of low-cost, low-power solutions is highlighted, which are increasingly being used in intelligent consumer equipment. Thanks to the great development of the automated design environments and fabrication methods, new, so far unknown applications of the vision chips become possible, as for example disposable endoscopy capsules for photographing the human gastrointestinal tract for the purposes of medical diagnosis.

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“…The integrators are library cells. In this realization, the modified version of the integrator presented in is used.…”

Section: Switched‐current Implementation Of Filter Pairsmentioning

confidence: 99%

VHDL‐AMS in switched‐current analog filter pair design based on a gyrator‐capacitor prototype circuit

Handkiewicz

Katarzyński

Szczęsny

et al. 2013

Int J Numerical Modelling

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SUMMARYThis paper presents an approach to a low-sensitivity design strategy for switched-current (SI) filter pairs based on a gyrator-capacitor prototype circuit. On the basis of a prototype filter, an SI counterpart circuit is obtained. Tools for SI filter design automation have been developed, which make a hardware description language -analog-mixed signal synthesization for the chosen kind of circuit. The obtained SI filter is better than the filter obtained using LC ladder structures with respect to very-large-scale integration complementary metal-oxide-semiconductor chip area and power consumption.

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Low power switched‐current circuits with low sensitivity to the rise/fall time of the clock

Cited by 10 publications

References 12 publications

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

Current-Mode FPAA with CMRR Elimination and Low Sensitivity to Mismatch

Analogue CMOS ASICs in Image Processing Systems

VHDL‐AMS in switched‐current analog filter pair design based on a gyrator‐capacitor prototype circuit

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