Low-power technology mapping for FPGA architectures with dual supply voltages

Abstract

In this paper we study the technology mapping problem of FPGA architectures with dual supply voltages (Vdds) for power optimization. This is done with the guarantee that the mapping depth of the circuit will not increase compared to the circuit with a single Vdd. We first design a single-Vdd mapping algorithm that achieves better power results than the latest published lowpower mapping algorithms. We then show that our dual-Vdd mapping algorithm can further improve power savings by up to 11.6% over the single-Vdd mapper. In addition, we investigate the best low-Vdd/high-Vdd ratio for the largest power reduction among several dual-Vdd combinations. To our knowledge, this is the first work on dual-Vdd mapping for FPGA architectures.

SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power

“…We show the detailed comparison results between SETmap, SVmap [16], and Emap [15] in terms of the power consumption and the soft error rate using both MCNC and ICSAS'89 benchmarks.…”

“…The power column is the power consumption reported by fpgaEVA-LP2. We compare to two previously published low-power technology mappers, SVmap [16] and Emap [15]. Both guarantee optimal mapping depth.…”

“…Experimental results show that our algorithm produces significant error rate reduction over previous low-power mapping algorithms, SVmap [16] and Emap [15], across a series of MCNC and ICSAS'89 benchmarks with ignorable power overhead. To the best of our knowledge, this is the first technology mapping algorithm that targets both soft-error reduction and low power for…”

“…There is previous work such as [11], [12], PowerMap [13], PowerMinMap [14], Emap [15], and SVmap/DVmap [16] on low-power FPGA technology mapping. Techniques including bin packing, dynamic programming, greedy algorithm, binate covering, network flow algorithm, and cut-enumeration algorithm have been applied to hide the nodes of high-switching activity into LUTs so the overall dynamic power can be reduced.…”

Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages

“…Specifically, DVmap-2 and SVmap-2 borrowed additional new techniques from [13] and applied them over the original algorithm DVmap and SVmap [14]. These techniques, namely, global duplication cost adjustment, input sharing, and slack distribution, have been helpful for area reduction during technology mapping in [13], and we use them here for the purpose of power reduction for both single-Vdd and dual-Vdd mapping.…”