Low standby power state storage for sub-130-nm technologies

Clark, Lawrence T.; Ricci, Franco; Biyani, Manish

doi:10.1109/jssc.2004.840987

Cited by 12 publications

(3 citation statements)

References 13 publications

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“…There are several different implementations of retention registers [Shigematsu et al 1997;Kao and Chandrakasan 2001;Zyuban and Kosonocky 2002;Won et al 2003;Clark et al 2005;Mair et al 2007;Lueftner et al 2007], some of which are shown in Figure 4. Figure 4(a) [Shigematsu et al 1997] shows a shadow latch, implemented in high-V t and not power-gated, while the remainder of the flip-flop is connected to a footer (or header) and is implemented in low-V t for performance.…”

Section: Storage Retentionmentioning

confidence: 99%

Power gating

Shin

Seomun

Choi

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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Power gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.

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Section: Storage Retentionmentioning

confidence: 99%

Power gating

Shin

Seomun

Choi

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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“…Since SRAMs often employ nonminimum channel lengths to improve matching and reduce leakage currents, there is no area penalty for the longer channel length. In contrast, logic circuits can use other methods to retain state, i.e., thick-gate shadow latches [11].…”

Section: B Drowsy Memoriesmentioning

confidence: 99%

Leakage Controlled Read Stable Static Random Access Memories

Badrudduza¹,

Wang

Samson

et al. 2008

JCP

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Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to addressing these problems are needed. Here, six and seven transistor SRAM cells are presented that do not suffer from reduced stability when read. The cells reside in a low leakage, voltage collapsed, low standby power mode when not being accessed. Both six transistor and seven transistor variations of the basic approach are explored through simulation and measured results. The circuit topology, layout, and impact on memory design of the proposed cell designs are described. Measured results on a 130 nm foundry fabrication process demonstrate the viability of three of the possible cell configurations. Circuit simulation is used to explore the cell stability in the presence of process variations, and to show the value of the proposed SRAM cell designs on future scaled manufacturing technologies.

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“…And the reduction of standby power is one of critical issues for low power LSI since the leakage current greatly increases with downscaling of technology node [1]- [3].…”

Section: Introductionmentioning

confidence: 99%

Highly Reliable Non-volatile Logic Circuit Technology and Its Application

Kimura

Zhong

Mizuochi

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYA ferroelectric-based (FE-based) non-volatile logic is proposed for low-power LSI. Standby currents in a logic circuit can be cut off by using FE-based non-volatile flip-flops (NVFFs), and the standby power can be reduced to zero. The FE capacitor is accessed only when the power turns on/off, performance of the NVFF is almost as same as that of the conventional flip-flop (FF) in a logic operation. The use of complementarily stored data in coupled FE capacitors makes it possible to realize wide read voltage margin, which guarantees 10 years retention at 85 degree Celsius under less than 1.5V operation. The low supply voltage and electro-static discharge (ESD) detection technique prevents data destruction caused by illegal access for the FE capacitor during standby state. Applying the proposed circuitry in CPU, the write and read operation for all FE capacitors in 1.6k-bit NVFFs are performed within 7μs and 3μs with access energy of 23.1nJ and 8.1nJ, respectively, using 130nm CMOS with Pb(Zr,Ti)O 3 (PZT) thin films. key words: non-volatile logic, non-volatile flip-flop, ferroelectric capacitor, high reliability, data protection

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Low standby power state storage for sub-130-nm technologies

Cited by 12 publications

References 13 publications

Power gating

Power gating

Leakage Controlled Read Stable Static Random Access Memories

Highly Reliable Non-volatile Logic Circuit Technology and Its Application

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