Low Thermal Budget Processing for Sequential 3-D IC Fabrication

Rajendran, Bipin; Shenoy, Rohit S.; Witte, D. J.; Chokshi, Nehal; Leon, R.; Tompa, Gary S.; Ruf, Fabian; Pease, W.

doi:10.1109/ted.2007.891300

Cited by 60 publications

(16 citation statements)

References 9 publications

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“…This method only results in localized heating, thereby preventing any damage to the devices and interconnects on the bottom tier. However, this process results in degraded transistors, and the PMOS and NMOS performance degrade by 27.8% and 16.2% respectively [8]. We refer to these degraded transistors as the T T m20p corner, as on average, the performance is worse by roughly 20%.…”

Section: Inter-tier Variationmentioning

confidence: 99%

Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations

Panth

Samadi

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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In this paper we study the power vs. performance tradeoff in blocklevel monolithic 3D IC designs. Our study shows that we can close the power-performance gap between 2D and a theoretical lower bound by up to 50%. We model the inter-tier performance variations caused by a low temperature manufacturing process on the non-bottom tiers. We also model an alternate manufacturing process, where highly resistive tungsten interconnects are used on the bottom tier to withstand a high temperature process on the nonbottom tiers. We propose a variation-aware floorplanning technique that makes our design more tolerant to these variations. We demonstrate that our design methods can help us obtain high quality designs even under inter-tier performance variations.

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Section: Inter-tier Variationmentioning

confidence: 99%

Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations

Panth

Samadi

et al. 2014

Proceedings of the 51st Annual Design Automation Conference

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“…In these devices, the PN junctions are vertical and obtained by the transfer of a predoped substrate. In the context of standard high performance MOSFET, i.e., with an horizontal channel, other techniques such as laser [22] or microwave annealing [23] are under investigation for the dopant activation step.…”

Section: Low Temperature Process (650 C) For Top Mosfetmentioning

confidence: 99%

3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS

Batude

Ernst

Arcamone

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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3-D sequential integration stands out from other 3-D schemes as it enables the full use of the third dimension. Indeed, in this approach, 3-D contact density matches with the transistor scale. In this paper, we report on the main advances enabling the demonstration of functional and performant stacked CMOS-FETs; i.e., wafer bonding, low temperature processes ( C) and salicide stabilization achievements. This integration scheme enables fine grain partitioning and thus a gain in performance versus cost ratio linked to separation of heterogeneous technologies on distinct levels. In this work, we will detail examples taking advantage of the unique 3-D contact pitch achieved with sequential 3-D.Index Terms-Low temperature process, molecular bonding, solid phase epitaxy, three-dimensional (3-D) integration, 3-D monolithic integration, 3-D sequential integration.

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“…In the periphery of such regular arrays of memory devices are CMOS logic circuits that allow controlled access to the memory cells for programming and reading the data stored in them. It is also worth mentioning that there are other exciting fabrication ideas that are pursued such as three-dimensional integration [162] and sub-lithographic cross-bar arrays [50] to enhance memory capacity beyond what is possible by conventional methods. Further, it is also typical to provide extra memory devices and associated decoding circuitry on each word-line for redundancy and error correction.…”

Section: Next Generation Memory Technologies -mentioning

confidence: 99%

“…Hence, it is ideal if the maximum temperature necessary for the integration of the memory device can be limited to 450 • C [162]. Typically, memory elements are integrated in the process flow after the completion of the fabrication steps for the CMOS devices, and this sets an upper limit to the thermal budget that the substrate can be subjected to, primarily to maintain the reliability of the semiconductor junctions and the low resistive silicide contacts of Typical memory systems are configured in a hierarchical manner, comprising of twodimensional arrays, with memory cells connected at the intersection of perpendicular metal lines, called 'bit-lines' and 'word-lines'.…”

Section: Next Generation Memory Technologies -mentioning

confidence: 99%