Low-voltage low-overhead asynchronous logic

Sridharan, Akshay; Sechen, Carl; Jafari, Roozbeh

doi:10.1109/islped.2013.6629306

Cited by 2 publications

(2 citation statements)

References 17 publications

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“…The delay in the subthreshold region varies by ~10X between the FF and SS corners and also under the MC runs the best and the worst case delays vary by 10X. We also tested our asynchronous scheme under the same MC variations and observed that the system adapted to it as reported in [7].…”

Section: A Observed Variationsmentioning

confidence: 98%

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Minimum energy operation using robust asynchronous logic with sleep transistors

Sridharan

Sechen

2014

2014 IEEE Dallas Circuits and Systems Conference (DCAS)

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We demonstrate minimum energy operation using a robust approach to asynchronous logic design combined with the use of sleep transistors. The combined approach yields extremely low power and energy for a system operating in the subthreshold regime. This enables operation at voltages below those associated with the previously proposed minimum energy operating point (MEP) and therefore appreciably reduces the energy consumption compared to MEP. We also demonstrate that the robustness of our asynchronous system under Monte Carlo variations can actually yield significant additional power savings compared to a synchronous design. Keywords-sleep, asynchronous design, low power, leakage energy, dynamic energy, minimum energy point, subthreshold.

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Section: A Observed Variationsmentioning

confidence: 98%

“…No extra circuit logic is needed to generate the sleep and active mode signals as would be needed for a synchronous system. The request signals in the asynchronous logic scheme of [7] is used for this purpose. In the absence of a rising edge of a request the logic block stays asleep.…”

Section: Letmentioning

confidence: 99%