Low voltage low power 4 bits digital to analog converter

Bchir, Mounira; Aloui, Imen; Hassen, Néjib; Besbes, Kamel

doi:10.1109/scc53769.2021.9768350

Cited by 1 publication

(1 citation statement)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The comparison of the overall energy efficiency of the MAC unit between various precision designs and NVM device benchmarks (Li et al, 2018;Joshi et al, 2020;Yao et al, 2020) is demonstrated in Figure 2D, according to the circuit module metrics in (Miyahara et al, 2011;Texas Instruments, 2011; Frontiers in Electronics frontiersin.org Rabuske et al, 2012;Mahdavi et al, 2017;Bchir et al, 2021).…”

Section: Quantization Precision and Hardware Overheadmentioning

confidence: 99%

Quantization and sparsity-aware processing for energy-efficient NVM-based convolutional neural networks

Bao¹,

Qin²,

Chen³

et al. 2022

Front.Electron.

View full text Add to dashboard Cite

Nonvolatile memory (NVM)-based convolutional neural networks (NvCNNs) have received widespread attention as a promising solution for hardware edge intelligence. However, there still exist many challenges in the resource-constrained conditions, such as the limitations of the hardware precision and cost and, especially, the large overhead of the analog-to-digital converters (ADCs). In this study, we systematically analyze the performance of NvCNNs and the hardware restrictions with quantization in both weight and activation and propose the corresponding requirements of NVM devices and peripheral circuits for multiply–accumulate (MAC) units. In addition, we put forward an in situ sparsity-aware processing method that exploits the sparsity of the network and the device array characteristics to further improve the energy efficiency of quantized NvCNNs. Our results suggest that the 4-bit-weight and 3-bit-activation (W4A3) design demonstrates the optimal compromise between the network performance and hardware overhead, achieving 98.82% accuracy for the Modified National Institute of Standards and Technology database (MNIST) classification task. Moreover, higher-precision designs will claim more restrictive requirements for hardware nonidealities including the variations of NVM devices and the nonlinearities of the converters. Moreover, the sparsity-aware processing method can obtain 79%/53% ADC energy reduction and 2.98×/1.15× energy efficiency improvement based on the W8A8/W4A3 quantization design with an array size of 128 × 128.

show abstract