LRPC Codes with Multiple Syndromes: Near Ideal-Size KEMs Without Ideals

Aguilar-Melchor, Carlos; Aragon, Nicolas; Dyseryn, Victor; Gaborit, Philippe; Zémor, Gilles

doi:10.1007/978-3-031-17234-2_3

Cited by 10 publications

(7 citation statements)

References 25 publications

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“…Thus, horizontal interleaving appears to be better suited for cryptographic purposes. This is also reflected in recent proposals as for example in the KEM LowMS [6] that is based on horizontally interleaved Gabidulin codes, in the signature scheme Durandal [5] based on the closely related rank-support-learning (RSL) problem [10], and in the cryptosystem [2] that makes use of horizontally interleaved low-rank parity-check (LRPC) codes [39].…”

Section: Introductionmentioning

confidence: 92%

“…We now derive a Gao-like decoder in the spirit of [20,45,36] for HILRS codes and the interleaved sum-rank-channel model described in (2). Let y = c + e ∈ F sn q m denote the received vector after the codeword c = c(f ) ∈ HILRS[β, ξ, s; sn, sk] was corrupted by the error e ∈ F sn q m of sum-rank weight wt ΣR (e) = t during transmission.…”

Section: A Gao-like Decoder For Hilrs Codesmentioning

confidence: 99%

“…. , s. Let further y = c + e ∈ F sn q m denote a channel observation according to (2). For the ESP σ ∈ F q m [x; θ, δ] and the polynomials…”

Section: A Gao-like Decoder For Hilrs Codesmentioning

confidence: 99%

“…Lemma 1. Consider a vector y = c + e ∈ F sn q m that was received after transmitting c ∈ HILRS[β, ξ, s; sn, sk] over the channel (2). Assume that the error has weight wt ΣR (e) = t ≤ n − k and can be decomposed into e = a • B according to (4).…”

Section: Algorithm 1: Gao-like Decoder For Hilrs Codesmentioning

confidence: 99%

“…Theorem 2 (Gao-like Decoding of HILRS Codes). Consider the transmission of a codeword c ∈ HILRS[β, ξ, s; sn, sk] over the channel (2). Let y = c + e ∈ F sn q m denote the received word and assume that the error e has bounded sum-rank weight…”

Section: ⊓ ⊔mentioning

confidence: 99%

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Interpolation-based decoding of folded variants of linearized and skew Reed–Solomon codes

Hörmann

Bartz

2023

Des. Codes Cryptogr.

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The sum-rank metric is a hybrid between the Hamming metric and the rank metric and suitable for error correction in multishot network coding and distributed storage as well as for the design of quantum-resistant cryptosystems. In this work, we consider the construction and decoding of folded linearized Reed–Solomon (FLRS) codes, which are shown to be maximum sum-rank distance (MSRD) for appropriate parameter choices. We derive an efficient interpolation-based decoding algorithm for FLRS codes that can be used as a list decoder or as a probabilistic unique decoder. The proposed decoding scheme can correct sum-rank errors beyond the unique decoding radius with a computational complexity that is quadratic in the length of the unfolded code. We show how the error-correction capability can be optimized for high-rate codes by an alternative choice of interpolation points. We derive a heuristic upper bound on the decoding failure probability of the probabilistic unique decoder and verify its tightness by Monte Carlo simulations. Further, we study the construction and decoding of folded skew Reed-Solomon codes in the skew metric. Up to our knowledge, FLRS codes are the first MSRD codes with different block sizes that come along with an efficient decoding algorithm.

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Section: Introductionmentioning

confidence: 92%

Section: A Gao-like Decoder For Hilrs Codesmentioning

confidence: 99%

“…. , s. Let further y = c + e ∈ F sn q m denote a channel observation according to (2). For the ESP σ ∈ F q m [x; θ, δ] and the polynomials…”

Section: A Gao-like Decoder For Hilrs Codesmentioning

confidence: 99%

Section: Algorithm 1: Gao-like Decoder For Hilrs Codesmentioning

confidence: 99%

Section: ⊓ ⊔mentioning

confidence: 99%

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Interpolation-based decoding of folded variants of linearized and skew Reed–Solomon codes

Hörmann

Bartz

2023

Des. Codes Cryptogr.

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Towards Automating Cryptographic Hardware Implementations: A Case Study of HQC

Aguilar-Melchor¹,

Deneuville²,

Dion³

et al. 2023

Lecture Notes in Computer Science

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While hardware implementations allow the production of highly efficient and performance oriented designs, exploiting features such as parallelization, their longer time to code and implement often bottlenecks rapid prototyping. On the other hand, high-level synthesis (HLS) tools allow for faster experimentation of software code to a hardware platform while demonstrating a reasonable extrapolation of the expected hardware behavior. In this work, we attempt to show a rapid, fast prototyping of the well known HQC algorithm, using HLS, and show how with a modification of certain parameters, varying degrees of comparable results can be obtained. These results, in turn, could be used as a guide for HDL-RTL developers to enhance their designs and better prototyping time in the future. Additionally, we also demonstrate that it is possible to benefit from HQC's versatility; by achieving a low hardware footprint whilst also maintaining good performances, even on low-cost FPGA devices, which we demonstrate on the well known Artix-7 xc7a100t-ftg256-1.

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