Machine Learning Prediction for 13X Endurance Enhancement in ReRAM SSD System

Iwasaki, Takaya; Ning, Sheyang; Yamazawa, Hiroki; Sun, Chuen-Tsai; Tanakamaru, Shuhei; Takeuchi, Ken

doi:10.1109/imw.2015.7150294

Cited by 11 publications

(9 citation statements)

References 2 publications

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“…Machine learning algorithms are the task of obtaining concrete information through data [4][5][6]. The machine learning algorithm proceeds in the following order.…”

Section: Machine Learningmentioning

confidence: 99%

SSD Garbage Collection Detection and Management with Machine Learning Algorithm

Park¹,

Kim²

2018

IJCA

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The garbage collection (GC) task of removing invalid pages due to insufficient free space on the flash memory chip inside the SSD has a significant impact on SSD performance. This GC operation is performed by the FTL, which is an internal firmware of the SSD, so that it is impossible to know whether the SSD is garbage collected at the operating system level. In this paper, we attempt to manage GC overhead at the operating system level. In our approach, first, we use a machine learning technique to devise a GC detecting mechanism at the operating system level, and second, we show that by making use of this mechanism performance variance normally observed on SSDs can be reduced. We develop a GC-detector that detects garbage collection of SSDs and request TRIM operations to the SSD when GC is detected. Experimental results running the GC-detector show increase average bandwidth and low performance variance compared to when not using GC-detector.

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“…Machine learning algorithms are the task of obtaining concrete information through data [4][5][6]. The machine learning algorithm proceeds in the following order.…”

Section: Machine Learningmentioning

confidence: 99%

SSD Garbage Collection Detection and Management with Machine Learning Algorithm

Park¹,

Kim²

2018

IJCA

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“…This implementation is suitable for the memories, such as ReRAM, for which endurance is limited due to cell wear-out and BER increase with write cycling [8]. In detail, 128 Bytes 50 nm Al x O y ReRAM cells in a 64 Mbits array are measured to verify the proposed scheme [7], [20]. Fig.…”

Section: Endurance Extensionmentioning

confidence: 99%

“…There are many possible causes of data error such as program disturb, data retention, memory cell wear-out, etc. [5], [7]- [9], [16]. Program errors are immediately evident after data program, whereas, retention errors occur after long retention times.…”

mentioning

confidence: 99%

“…Compared to NRAM, which has high cycling endurance, program error increases with cycling in Al x O y ReRAM, and therefore limits ReRAM's endurance. In this paper, 128 Bytes 50 nm Al x O y ReRAM cells in a 64 Mbit array [7] are measured, and compared to the conventional BCH ECC-only method, endurance extension of 50-times is obtained with the combined RCRF and BCH ECC. In this comparison, it is assumed that both methods use the same area overhead.…”

mentioning

confidence: 99%

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Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Ning

Iwasaki

Tanakamaru

et al. 2016

IEEE J. Solid-State Circuits

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A novel error correction scheme, called reset-checkreverse-flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10 8 write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm Al x O y resistive RAM (ReRAM) test chip.Index Terms-Carbon nanotube, emerging memory, error correcting code, memory controller, non-volatile memory, NRAM, reliability, solid-state drive, storage class memory.

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“…To improve the SSD performance, hybrid SSDs using the NAND flash memories or storage-class memories (SCMs) have been proposed. [13][14][15][16][17][18][19][20][21][22][23][24][25] The SCMs are non-volatile and able to be accessed by byte unit, thus read=write latencies of SCMs are much faster than those of NAND flash memories. Utilizing SCMs as a non-volatile cache or small-capacity storage to store frequent accessed data, performance of SSDs can be accelerated drastically.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

Sakaki¹,

Yamada²,

Matsui³

et al. 2018

Jpn. J. Appl. Phys.

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In order to improve performance of solid-state drives (SSDs), hybrid SSDs have been proposed. Hybrid SSDs consist of more than two types of NAND flash memories or NAND flash memories and storage-class memories (SCMs). However, the cost of hybrid SSDs adopting SCMs is more expensive than that of NAND flash only SSDs because of the high bit cost of SCMs. This paper proposes unique hybrid SSDs with twodimensional (2D) horizontal multi-level cell (MLC)/three-dimensional (3D) vertical triple-level cell (TLC) NAND flash memories to achieve higher cost-performance. The 2D-MLC/3D-TLC hybrid SSD achieves up to 31% higher performance than the conventional 2D-MLC/2D-TLC hybrid SSD. The factors of different performance between the proposed hybrid SSD and the conventional hybrid SSD are analyzed by changing its block size, read/write/erase latencies, and write unit of 3D-TLC NAND flash memory, by means of a transaction-level modeling simulator.

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Machine Learning Prediction for 13X Endurance Enhancement in ReRAM SSD System

Cited by 11 publications

References 2 publications

SSD Garbage Collection Detection and Management with Machine Learning Algorithm

SSD Garbage Collection Detection and Management with Machine Learning Algorithm

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Performance analysis of three-dimensional-triple-level cell and two-dimensional-multi-level cell NAND flash hybrid solid-state drives

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