mAgic-FPU and MADE: A customizable VLIW core and the modular VLIW processor architecture description environment

Paolucci, P.; Kajfasz, Philippe; Bonnot, Philippe; Candaele, Bernard; Maufroid, Daniel; Pastorelli, Elena; Ricciardi, Andrea; Fusella, Yves; Guarino, Eugenio

doi:10.1016/s0010-4655(01)00235-1

Cited by 9 publications

(6 citation statements)

References 11 publications

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“…As LE1 supports pure hardware threads, this seed code was taken through the LE1 tool-chain (VEX Compiler, Assembler and cycle-accurate Simulator) in the process, modeling multiple hardware configurations. The configurations studied include various VLIW issue widths (2,4,8-wide), variable number of threads (1,2,4,8) and variable number of memory banks (1,2,4,8). For multi-bank simulations, the number of memory banks was chosen always less then or equal to the number of threads.…”

Section: Performance Evaluationmentioning

confidence: 99%

“…These accelerators occasionally are custom VLIW engines as the VLIW architectural paradigm [3] seems to be the most promising in delivering very high single-processor performance, particularly on data-parallel inner loops; interestingly enough, such processors seem to be finding niche markets in behavioral (ESL) synthesis as a core component of the underlying VLSI platform [4]. The research area of custom, multi-parallel programmable embedded architectures is quite broad and some notable examples of relevant research can be found in [5] [6][7] [8]. Supporting hardware primitives for on-chip multiprocessing is a particularly interesting area of research; The authors report in [9] on a custom coprocessor for FPGA-based systems, able to implement efficiently Remote Memory Access (RMA) primitives in message-passing systems.…”

Section: Introductionmentioning

confidence: 99%

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LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

Stevens

Chouliaras

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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We discuss LE1, a parameterized VLIW Chip Multiprocessor (CMP) adhering to the shared memory programmers model. LE1's novelty lies in its ability to perform dynamic thread-spawning through hardware support for PThread-like primitives in addition to its substantial architectural and microarchitectural parameterization. Dynamic (hardware) thread creation is very fast and removes the need for an executive/OS, presenting to the application programmer a 'bare-metal' multiprocessor, capable of exploiting all forms of parallelism. The core LE1 CPU is a configurable, 8-stage pipeline VLIW engine with a proprietary Instruction Set Architecture (ISA) supporting both partial and full predication and pipelined, multi-input, multi-output (MIMO) instruction extensions. The LE1 CMP is parameterizable as to the number of processors, their issue capability, internal microarchitectural features, functional unit mix and latency and the local memory system architecture.Preliminary results indicate near-linear performance improvement when executing a threaded version of the Mandelbrot calculation on 2-way and 4-way processor configurations with a 256 KB, 4-way banked tightly-coupled memory system. Similar trends are seen when executing a threaded matrix multiplication benchmark. We present these findings along with VLSI implementations of 4-way, dual-issue and 3-way, quad issue multiprocessor configurations.

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Section: Performance Evaluationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

Stevens

Chouliaras

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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“…Babel is also utilized to retarget the SimpleScalar simulator [62]. MADE: The modular VLIW processor architecture and assembler description environment (MADE) [206] generates a library of behavioral functions and the instruction-set of the machine from the related architecture description. The library is then linked to a reconfigurable scheduling engine which results in a configured optimizer-scheduler.…”

Section: Other Related Approachesmentioning

confidence: 99%

C Compilers for ASIPs

Hohenauer

Leupers

2010

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“…Each tile can be equipped with a Distributed eXternal Memory (DXM). The tile is the evolution of Atmel Diopsis [7], a multiprocessor SoC which includes a RISC + the floating-point VLIW mAgic DSP [11].…”

Section: Introduction 11 the Tiled Hw Architecture Of Shapesmentioning

confidence: 99%

“…The classical drawback of VLIW architectures is that the longer instruction words require more memory. While conventional code compression /decompression schemes mitigate this problem [10][11], they also increase control logic overhead. We solved this problem by developing in hardware a small footprint (18 Kgate) VLIW Dynamic Program memory Decompression system (DyProDe).…”

Section: Introduction 11 the Tiled Hw Architecture Of Shapesmentioning

confidence: 99%

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Paolucci

Jerraya

Leupers

et al. 2006

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis

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Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. Tiled architectures suggest a possible path: "small" processing tiles connected by "short wires". A typical SHAPES tile contains a VLIW floating-point DSP, a RISC, a DNP (Distributed Network Processor), distributed on chip memory, the POT (a set of Peripherals On Tile) plus an interface for DXM (Distributed External Memory). The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours engineering methodologies is adopted for off-chip networking and maximum system density. The SW challenge is to provide a simple and efficient programming environment for tiled architectures. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and intertile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface.

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mAgic-FPU and MADE: A customizable VLIW core and the modular VLIW processor architecture description environment

Cited by 9 publications

References 11 publications

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support

C Compilers for ASIPs

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