Managing power and performance for system-on-chip designs using Voltage Islands

Lackey, D.E.; Zuchowski, P.S.; Bednar, T.R.; Stout, D.W.; Gould, S.W.; Cohn, J.M.

doi:10.1109/iccad.2002.1167534

Cited by 102 publications

(90 citation statements)

References 7 publications

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“…The supply voltage of MCD may be uniform. If the voltage level differs between the domains, the hardware design is in MVD or multiple voltage islands [14]. To support the required throughput with lower power consumption in the design with multiple voltage domains, techniques such as CG, PG, FS, and DVFS could be applied.…”

Section: Low-power Designmentioning

confidence: 99%

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Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

et al. 2007

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Dynamic voltage scaling (DVS) and power gating (PG) have become mainstream technologies for low-power optimization in recent years. One issue that remains to be solved is integrating these techniques in correlated domains operating with multiple voltages. This article addresses the problem of power-aware task scheduling on a scalable cryptographic processor that is designed as a heterogeneous and distributed system-on-a-chip, with the aim of effectively integrating DVS, PG, and the scheduling of resources in multiple voltage domains (MVD) to achieve low energy consumption. Our approach uses an analytic model as the basis for estimating the performance and energy requirements between different domains and addressing the scheduling issues for correlated resources in systems. We also present the results of performance and energy simulations from transaction-level models of our security processors in a variety of system configurations. The prototype experiments show that our proposed methods yield significant energy reductions. The proposed techniques will be useful for implementing DVS and PG in domains with multiple correlated resources.

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Section: Low-power Designmentioning

confidence: 99%

“…The main difficulty in PG technology is issuing off/on commands at the appropriate times so as to minimize performance degradation and maximize the reduction in leakage power [9][10][11][12][13]. In its use of MVD or voltage islands [14], PG also gives more opportunity to reduce the voltage consumption at each decomposed power domain.…”

Section: Introductionmentioning

confidence: 99%

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

et al. 2007

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“…Notice that this effect could be avoided by implementing Voltage and Frequency Islands (VFIs) [55][56]. However, this would imply extra silicon area and power to implement the VFIs separate DVFS controllers, and it would require to either know at design-time where hotspots will be located, or the ability to confine the hotspot traffic in a separate voltage island at run-time.…”

Section: Analysis Of the Dmsd Dvfs Policymentioning

confidence: 99%

“…Recent proposals shadow this effect by setting different DVFS regions, called Voltage and Frequency Islands (VFIs) [55] [56]. In this way, frequency and voltage for a given island become independent as they are only driven by the metrics obtained from such island.…”

Section: Introductionmentioning

confidence: 99%

“…In this way, frequency and voltage for a given island become independent as they are only driven by the metrics obtained from such island. From the efficiency point of view, VFI islands achieve an undeniable enhancement [55] as applications running concurrently may have different needs, some maximizing performance while others minimizing power. Nonetheless, VFIs still pose new challenges.…”

Section: Introductionmentioning

confidence: 99%

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Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

López¹,

José²

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Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Circuit Theory & Apps

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Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire-bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi-voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time-consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency.decoupling capacitors configuration to alleviate the power delivery noise [12,13]. However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20]. Hence, designers typically limit the voltage drops within 10% of the supply voltage to guarantee faultless operation [21]. Lower supply voltage indicates that lower noise margins or smaller voltage drops are permitted on the P/G network [22]. For instance, 1.5-V supply voltages permit 150-mV voltage drop while 1.0-V supply voltages only allow 100-mV voltage drop. Compared with single-voltage SoC, the voltage drop constraints present more challenges for the P/G network design of the multi-voltage SoC. First, from a low-power perspective, a VI with a larger area and a lower supply voltage is preferred during the VI generation process. However, the permitted ultra-low voltage drops make the P/G network hard to design. Second, power pads are located at the periphery of the chip for wire-bonding package. Locations of power pads affect both the timing and voltage drops [23]. Although multiple power pads for each VI can leverage the voltage drops, it may not be practical because the power pads must compete with other signal I/Os under the limited pad resource. Thus, it is vital to consider voltage drops in P/G network design for multi-voltage SoC. Related workConsid...

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Managing power and performance for system-on-chip designs using Voltage Islands

Cited by 102 publications

References 7 publications

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

Energy-aware scheduling and simulation methodologies for parallel security processors with multiple voltage domains

Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

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