Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays

Abstract

Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rely heavily on centralized storage, e.g. register files and embedded memories, spatial processors require many small storage structures to efficiently manage values that are distributed throughout the processor's fabric. The goal of this work is to determine the advantages and disadvantages of different architectural structures for storing values on-chip when optimizing for energy efficiency as well as area.Examination of applications for coarse-grained reconfigurable arrays (CGRAs) shows that most values are short-lived; they are produced and consumed quickly, but the distribution of value lifetimes has a reasonably long tail. We take advantage of this distribution to optimize register storage structures for managing short-, medium-, and long-lived values.We show that using a combination of register storage structures, each tailored for values with different lifetimes, provides a reduction in overall area-energy product to 0.69× the area-energy of the baseline architecture, without loss of performance. Finally we provide energy profiles, characteristics, and comparisons of each register structure to enable architects to guide future design choices.

A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

“…These fabrics used pas from one stripe to the other. [22] describes how to manage short coarse-grained fabrics. They discuss various architectural options for storing values when optimizing for area and energy.…”

Energy-efficient specialization of functional units in a coarse-grained reconfigurable array

“…This experiment uses the benchmark suite as detailed in [3] and [4]. Table 1 shows the breakdown of operations within the benchmark suite, as well as an average frequency for each class of operation.…”

“…The Mosaic CGRA architecture (shown in [4]) is a cluster-based architecture that is arranged as a 2-D grid. To minimize the design complexity, the clusters are homogenous in the set of functional units that are supported.…”

“…This work builds upon the Mosaic research infrastructure and optimized architectures that were designed in [3] and [4]. Furthermore, this work uses the same suite of benchmarks and 65nm process for the architecture's physical models as [4].…”

“…Furthermore, this work uses the same suite of benchmarks and 65nm process for the architecture's physical models as [4].…”