Manufacturability considerations for DSA

Farrell, Richard A.; Hosler, Erik R.; Schmid, Gerard M.; Xu, Jianzhong; Preil, Moshe E.; Rastogi, Vinayak; Mohanty, Nihar; Kumar, Kaushik; Cicoria, Michael; Hetzer, David; Devilliers, Anton

doi:10.1117/12.2048396

Cited by 13 publications

(9 citation statements)

References 7 publications

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“…4,5 These include variations on thermal and solvent annealing, substrate patterning (grapho-/chemoepitaxy), 6 and a variety of thermal, mechanical, and electromagnetic gradient-based approaches. 4,7 Despite extensive study, key challenges remain in balancing processing complexity (and cost) with the increasing demands for precisely tailored microstructure for lithography 8 and emerging areas such as energy generation/storage, 9 nanoparticle scaffolds, 10 and novel optical applications. 11…”

Section: Introductionmentioning

confidence: 99%

Rapid, interface-driven domain orientation in bottlebrush diblock copolymer films during thermal annealing

et al. 2022

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Section: Introductionmentioning

confidence: 99%

Rapid, interface-driven domain orientation in bottlebrush diblock copolymer films during thermal annealing

et al. 2022

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“…The EBAC system revealed the line breaking with approximately 25 nm in length on the metal wire line pattern with 9 nm in width. It is considered that the line breaking was caused by the short defect, so called the grid defect [29][30][31][32][33]. Figure 9 shows defect classification of the metal wire circuits with 9 nm in width.…”

Section: Resultsmentioning

confidence: 99%

Fabrication of Sub-10 nm Metal Wire Circuits using Directed Self-Assembly of Block Copolymers

Azuma

Seino

Sato

et al. 2016

J. Photopol. Sci. Technol.

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A novel half-pitch (HP) 10 nm physical-epitaxial frequency multiplication process using a high chi (χ) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrically open and short process level-test element group (PL-TEG) yield verification of sub-10 nm metal wire circuits fabricated using the HP 10 nm physical-epitaxial frequency multiplication process was carried out on a 300 mm wafer. The electrically open and short PL-TEG yield verification revealed the viability of the HP 10 nm physical-epitaxial frequency multiplication process from the perspective of the total practical performance including critical dimension control, defect control, pattern placement error, space width roughness, space edge roughness, and process windows in the pattern transfer process.

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“…There is inevitable demand for alternative patterning strategies which involve augmentation of 193i lithography with LELE (Litho-Etch-Litho-Etch), SADP (Self Aligned Double Patterning) and SAQP (Self Aligned Quadruple Patterning). [2][3][4][5] However, multiple patterning schemes bring in additional challenges in the form of Edge Placement Error, Higher Costs due Line Edge /Width Roughness / LCDU Line Collapse / Scummed or…”

Section: Introductionmentioning

confidence: 99%

Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)

et al. 2015

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Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process.In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

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Manufacturability considerations for DSA

Cited by 13 publications

References 7 publications

Rapid, interface-driven domain orientation in bottlebrush diblock copolymer films during thermal annealing

Rapid, interface-driven domain orientation in bottlebrush diblock copolymer films during thermal annealing

Fabrication of Sub-10 nm Metal Wire Circuits using Directed Self-Assembly of Block Copolymers

Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)

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