Mapping DSP Applications onto Self-timed Multiprocessors

Abstract

BackgroundMultiprocessor implementation of DSP applications involves the interaction of several complex factors including scheduling, interprocessor communication, synchronization, iterative execution, and more recently, voltage scaling for low power implementation. Addressing any one of these factors in isolation is itself typically intractable in any optimal sense; at the same time, with the increasing trend toward multi-objective implementation criteria in the synthesis of embedded software, it is desirable to understand the joint impact of these factors. In this paper, we examine several high-level, intermediate representations that have been developed to analyze and optimize various multiprocessor DSP implementation factors and manage their interactions.The techniques discussed in this paper pertain to system specifications based on iterative synchronous dataflow (SDF) graphs [9]. Iterative SDF programming of DSP applications has been researched widely in the context of multiprocessor implementation, and numerous commercial DSP tools have been developed that incorporate SDF semantics. Examples of such tools include SPW by Cadence, COSSAP by Synopsys, and ADS by Hewlett-Packard.In SDF, an application is represented as a directed graph in which vertices (actors) represent computational tasks, edges specify data dependences, and the numbers of data values (tokens) produced and consumed by each actor is fixed. Delays on SDF edges represent initial tokens, and specify dependencies between iterations of the actors in iterative execution. For example, if tokens produced by the th invocation of actor are consumed by the th invocation of actor , then the edge contains two delays. Actors can be of arbitrary complexity. In DSP design environments, they typically range in complexity from basic operations such as addition or subtraction to signal processing subsystems such as FFT units and adaptive filters. We refer to an SDF representation of an applications an application graph.In this paper, we use a form of SDF called homogeneous SDF (HSDF) that is suitable for dataflow-based multiprocessor design tools. In HSDF, each actor transfers a single token to/from each incident edge. General techniques for converting SDF graphs into HSDF are developed in [9]. We refer to a homogeneous SDF graph as a dataflow graph (DFG). We represent a DFG by an ordered pair , where is the set of actors and is the set of edges. We refer to the source and sink actors of a DFG edge by and , we denote the delay on by , and we frequently represent by the ordered pair . We say that is an output edge of ; is an input edge of ; and is delayless if . The execution time or estimated execution time of an actor is denoted . Mapping an application graph onto a multiprocessor architecture includes three important steps -assigning actors to processors (processor assignment), ordering the actors assigned to each processor (actor ordering), and determining when each actor should commence execution. All of these tasks can either be performed at run...