Mapping Statecharts to Verilog for Hardware/Software Co-specification

Abstract

The full-text may be used and/or reproduced, and given to third parties in any format or medium, without prior permission or charge, for personal research or study, educational, or not-for-prot purposes provided that:• a full bibliographic reference is made to the original source • a link is made to the metadata record in DRO • the full-text is not changed in any way The full-text must not be sold in any format or medium without the formal permission of the copyright holders.Please consult the full DRO policy for further details. Abstract. Hardware-Software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions in Verilog. In this paper, we investigate the Statecharts formalism by providing it a formal syntax and a compositional operational semantics.After that, we design a semantics-preserving mapping function to transform a Statecharts description into Verilog specification. We can combine this mapping with our previous formal partitioning process so as to form a more complete and automated co-specification process.

An Automatic Mapping from Statecharts to Verilog

“…In this paper, we use the formal syntax of statechart from [7] and [18]. The syntax of Statecharts formula is defined as follows (quoting from [18]): S : a set of names used to denote Statecharts. This is expected to be large enough to prevent name conflicts.…”

“…A term-based syntax of statecharts was introduced in [18] and [14], [15]. We reintroduce it here for the benefit of the reader.…”

“…[11], [10]. In our work, we shall use a behaviourial subset of Verilog introduced in [10] and [18]. This more abstract version of Verilog can be used to express designs at various levels of hardware behaviour.…”

“…This is obviously very desirable if one is to exploit the inherently parallel behaviour of hardware. In this work, we will make use of abstract Verilog [10], [18], that is described in the next chapter.…”

“…The compilation from Statecharts to Verilog can be embedded into the hardware/software co-specification process [19]. A mapping algorithm will be given in the following sections, where the soundness has been given in Qin and Chin [18].…”