MARTE and IP-XACT Based Approach for Run-Time Scalable NoC

Kidane, Hiliwi Leake; Bourennane, El-Bay

doi:10.1109/mcsoc2018.2018.00036

Cited by 3 publications

(2 citation statements)

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“…The number of routers in NoC depends on the network type, architecture with relatively more routers, are based on second group type of network, fast prototyping and virtualization. We have used the direct mapping network type in our previous works due to relatively high execution frequency [24,25]. These evaluation platforms assist the designers to reach the design-specific communication architecture, meeting most of the requirement specifications, for a certain application.…”

Section: Revisiting the Network On Chip Evaluation Toolsmentioning

confidence: 99%

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Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020

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Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

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Section: Revisiting the Network On Chip Evaluation Toolsmentioning

confidence: 99%

“…Single FPGA [4,76,77,86,87,106,107,109,115,117,118,125] [ 23,25,75,78,79,[84][85][86]89,107] Multiple FPGAs [4,77,87,106,115,117,125] [41,75,78,79]…”

Section: Single Application Multiple Applicationsmentioning

confidence: 99%