Matrix engine for signal processing applications using the logarithmic number system

Chester, Ed; Coleman, J.N.

doi:10.1109/asap.2002.1030730

Cited by 13 publications

(8 citation statements)

References 10 publications

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“…The fixedpoint representation of the antilogarithm is composed of the six most significant bits representing the integer part and the remaining 26 bits of the fractional part representing as given in (5). This value is divided into two parts, according to the positive or the negative input : (5) where and values are replaced when is a negative value in order to make the fractional part a positive value. Thus, and are modified to and as given by the following first two equations: (6) where (7) (8) where Executing the variable number range, the final integer part result is modified to which is equals to by the number range selection value .…”

Section: Antilogarithmic Converter Blockmentioning

confidence: 99%

“…Also, for the low power consumption, the clock cycles of these complex functions should be reduced as much as possible. Manuscript The logarithmic number system (LNS) has been studied to simplify arithmetic computations for lower computation complexity, high computation speed, and small gate counts [5]- [13]. Although there is conversion overhead from integer to logarithm or logarithmic to integer, the overhead is much smaller than that of conventional computation hardware.…”

Section: Introductionmentioning

confidence: 99%

“…Although there is conversion overhead from integer to logarithm or logarithmic to integer, the overhead is much smaller than that of conventional computation hardware. For this reason, there were trials to use the LNS for DSP applications [5], [6]. However, they performed the addition and subtraction operations in a nonlinear function like LNS, which make them more complicated and result in slow operation speed and high power consumption.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System

Kim

Nam

Sohn

et al. 2006

IEEE J. Solid-State Circuits

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Section: Antilogarithmic Converter Blockmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System

Kim

Nam

Sohn

et al. 2006

IEEE J. Solid-State Circuits

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“…Swartzlander et al [27,26] and others [19,12] reconsidered these algorithms and found them quite attractive in light of the technology available for digital signal processing in the 1970s. Beyond simple table lookup, several implementations [21,8,7,6] have provided SLNS arithmetic with increased performance and reduced implementation cost. In particular SLNS appears to offer reduced power consumption in many applications [25,23].…”

Section: Inriamentioning

confidence: 99%

Options for Denormal Representation in Logarithmic Arithmetic

Arnold¹,

Collange

2014

J Sign Process Syst

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International audienceEconomical hardware often uses a FiXed-point Number System (FXNS), whose constant absolute precision is acceptable for many signal-processing algorithms. The almost-constant relative precision of the more expensive Floating-Point (FP) number system simplifies design, for example, by eliminating worries about FXNS overflow because the range of FP is much larger than FXNS for the same wordsize; however, primitive FP introduces another problem: underflow. The Signed Logarithmic Number System (SLNS) offers similar range and precision as FP with much better performance (in terms of power, speed and area) for multiplication, division, powers and roots. This paper proposes three variations of a new number system, respectively called the Denormal LNS (DLNS), Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), which are all hybrids of the properties of FXNS and SLNS. The inspiration for D(OM)LNS comes from the denormal (aka subnormal) numbers found in IEEE-754 (that provide better, gradual underflow) and the μ-law often used for speech encoding; the novel DLNS circuit here allows arithmetic to be performed directly on such encoded data. The proposed approach allows customizing the range in which gradual underflow occurs. Our first DLNS implementation leverages existing SLNS basic blocks. Synthesis shows the novel circuit primarily consists of traditional SLNS addition and subtraction tables, with additional datapaths that allow the novel arithmetic unit to act on conventional SLNS as well as DLNS and mixed data, for a worst-case area overhead of 26 %. Unlike SLNS, this DLNS implementation is still costly for general (non-constant) multiplication, division and roots. To overcome this difficulty, this paper proposes the other variations called Denormal Mitchell LNS (DMLNS) and Denormal Offset Mitchell LNS (DOMLNS), in which the well-known Mitchell’s method makes the cost of general multiplication, division and roots closer to that of SLNS. Taylor-series computations suggest subnormal values in DMLNS and DOMLNS also behave similarly to those in the IEEE-754 FP standard. Synthesis shows that DMLNS and DOMLNS respectively have average area overheads of 25 % and 17 % compared to an equivalent SLNS 5-operation unit

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“…For the Fast Fourier Transform (FFT) in [3] it is shown that an LNS implementation uses a smaller word size than a comparable fixed-point system, while achieving the same error performance. LNS has also been used for matrix [4] and filter [5] applications. Bleris et al [6] show that a 16-bit LNS Application-Specific Integrated Processor (ASIP) is capable of implementing Model Predictive Control (MPC) in embedded applications, a possibility hindered previously by the high computational requirements of MPC using FP arithmetic.…”

Section: Introductionmentioning

confidence: 99%

A Novel Cotransformation for LNS Subtraction

Vouzis

Collange

Arnold

2008

J Sign Process Syst

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The Logarithmic Number System (LNS) can be considered a simplification of the Floating Point (FP) Number System that assumes the mantissa is always equal to one, and has a binary fixed-point exponent. LNS converts multiplication/division to a single addition/subtraction, which make LNS a very attractive choice for applications where these operations predominate, such as in some signal-processing algorithms. However, for wordlengths greater than 20 bits LNS becomes expensive because of the hardware-demanding LNS operations of addition and subtraction, which are typically important for most signal-processing algorithms. This paper gives an overview of the family of LNS subtraction algorithms called "Cotransformations," and proposes a "Novel Cotransformation Combination" that offers improvements in terms of area and speed without sacrificing accuracy compared to previous methods. The hardware requirements of the proposed method are analyzed mathematically, and the results are verified by using synthesis and simulations.

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Matrix engine for signal processing applications using the logarithmic number system

Cited by 13 publications

References 10 publications

A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System

A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System

Options for Denormal Representation in Logarithmic Arithmetic

A Novel Cotransformation for LNS Subtraction

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