Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Gupte, Ajit; Amrutur, Bharadwaj; Mehendale, Mahesh; Rao, A.V.; Budagavi, Madhukar

doi:10.1109/tcsvt.2011.2105599

Cited by 43 publications

(25 citation statements)

References 11 publications

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“…In this section, the generalized compression method for bus data in various bandwidth scenarios (8,16, and 32 bits) is described in detail with reference to Fig.2 through Fig. 4.…”

Section: Bus Data Compression Methods and Its Hardware Implementamentioning

confidence: 99%

See 1 more Smart Citation

A Bus Data Compression Method on a Phase-Based On-Chip Bus

Lee¹

2012

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec -1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively Index Terms-System-on-chip, on-chip bus, multimedia processor, VC-1 codec, video processor

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“…In this section, the generalized compression method for bus data in various bandwidth scenarios (8,16, and 32 bits) is described in detail with reference to Fig.2 through Fig. 4.…”

Section: Bus Data Compression Methods and Its Hardware Implementamentioning

confidence: 99%

“…S. Hong et al [15] made a special effort to reduce the limitation. A. Gupte et al [16] considered power consumption as well as the detraction problem.…”

Section: Related Workmentioning

confidence: 99%

A Bus Data Compression Method on a Phase-Based On-Chip Bus

Lee¹

2012

JSTS:Journal of Semiconductor Technology and Science

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“…Many previous works, where can be classified into three methods, have been proposed to achieve these two targets. Lossless and lossy compression methods [3,4] are proposed to minimize reference sample access. Advanced address mapping, arbitration, and controller scheduling [5] methods are proposed to improve memory access efficiency.…”

Section: Introductionmentioning

confidence: 99%

Memory interface design for AVS HD video encoder with Level C+ coding order

Huang

Wei

Xiang

et al. 2017

IEICE Electron. Express

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In video encoder chip, memory interface design is a must to transfer various data between the encoder pipeline and the off-chip memory. Reducing the required off-chip memory bandwidth and improving the memory access efficiency are the two key targets for optimized memory interface design. To achieve these two targets, three novel technologies are proposed in Level C+ coding order based AVS HD video encoder. Firstly, an improved Level C+ coding order with necessary NOP insertions are proposed to achieve 61% bandwidth reduction and make MB pipeline scheduling regular. Secondly, MB-level synchronous memory interface design is proposed by trading off external bandwidth, MB pipeline structure, and internal buffer size. Finally, address mapping and arbitration are proposed to improve the access efficiency by 12%. The optimized memory interface design is successfully implemented on our 1080P@45fps AVS encoder with Xilinx Virtex-6 FPGA at an operating frequency of 200 MHz.

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“…However, since reference frames used in an encoder becomes slightly different from those in a decoder due to coding error of reference frame compression, the lossy compression approach can cause drift. In [7], lossy compression uses in motion estimation, and lossless compression is used in motion compensation to avoid the drift. This is achieved by separately storing the quantization error in the lossy compression.…”

Section: Introductionmentioning

confidence: 99%

“…1(a). This sliding window approach updates only three macroblocks for each macroblock encoding [7]. When the shared internal memory is big enough to store several macroblock rows, external memory access can be reduced further as in Fig.…”

Section: Introductionmentioning

confidence: 99%

Memory bandwidth reduction using frame pipeline in video codec chips

Lee

Kim

2014

IEICE Electron. Express

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An image processing chip includes many image processing engines requesting heavy external memory access. So bus traffic is a critical issue in real-time systems. An video encoder is one of blocks requesting the most heavy external memory access among them. This letter presents a method to reduce the external memory requests for accessing reference frames in video codec chips. The method pipelines a video in a frame level, and the intermediate reconstructed data is used in the next frame without storing it to external memory. Thereby the proposed algorithm reduces the external memory access with reasonable internal memory increase.

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Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding

Cited by 43 publications

References 11 publications

A Bus Data Compression Method on a Phase-Based On-Chip Bus

A Bus Data Compression Method on a Phase-Based On-Chip Bus

Memory interface design for AVS HD video encoder with Level C+ coding order

Memory bandwidth reduction using frame pipeline in video codec chips

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