Memristive logic: A framework for evaluation and comparison

Reuben, John; Ben-Hur, Rotem; Wald, Nimrod; Talati, Nishil; Ali, Ameer Haj; Gaillardon, Pierre-Emmanuel; Kvatinsky, Shahar

doi:10.1109/patmos.2017.8106959

Cited by 81 publications

(63 citation statements)

References 23 publications

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“…The latter is considered a requirement for real in-/near-memory computing, since the topology of the logic circuits to implement should fit in the crossbar memory array, which is most likely the prevailing topology for memristive memory. What is more, the metrics proposed so far for the comparison of such logic families naturally focus on latency, energy, and area efficiency [20]. However, most such relevant works omit crucial factors such as variability (both cycle-to-cycle and device-to-device) and endurance of memristors; being the latter a major limitation to be considered if frequent switching is necessary during computations.…”

Section: Introductionmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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The advent of the first TiO2-based memristor in 2008 revived the scientific interest both from academia and industry for this device technology and has so far led to several emerging applications including logic and in-memory computing. Several memristive logic families have been proposed in the current quest for energy-efficient future computing systems. However, the limited device endurance and variability (both cycleto-cycle and device-to-device) are important parameters to be considered in the assessment of logic operations. In this work we used an accurate physics-based model of a bipolar memristor (supporting parasitics of the device structure and variability of switching voltages and resistance states) and demonstrate that performance of memristor-based in-memory computations can de degraded owing to both variability and state drift impact, if such features are not properly considered in the design flow. Inspired on pseudo-NMOS ratioed logic and based upon a CMOS-like logic scheme, we propose a crossbar-compatible memristive ratioed logic style which is tolerant to device variability and does not affect device endurance as computations do not involve conditional switching of memristors. Using the Cadence Virtuoso suite, we compare this logic scheme with MAGIC and CNIMP approaches, focusing on the universal NOR gate and complex logic functions.

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Section: Introductionmentioning

confidence: 99%

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Escudero

Vourkas

Rubio

et al. 2019

IEEE Trans. Nanotechnology

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“…In-memory evaluation of bitwise logic operations has been explored for memristive memories [48]- [50] and DRAM [51]. Our work differs from these efforts in several important aspects.…”

Section: Fig 1: Related Work: Overviewmentioning

confidence: 99%

Computing in Memory With Spin-Transfer Torque Magnetic RAM

Jain

Ranjan

Roy

et al. 2018

IEEE Trans. VLSI Syst.

291

187

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Abstract-In-memory computing is a promising approach to addressing the processor-memory data transfer bottleneck in computing systems. We propose Spin-Transfer Torque Computein-Memory (STT-CiM), a design for in-memory computing with Spin-Transfer Torque Magnetic RAM (STT-MRAM). The unique properties of spintronic memory allow multiple wordlines within an array to be simultaneously enabled, opening up the possibility of directly sensing functions of the values stored in multiple rows using a single access. We propose modifications to STT-MRAM peripheral circuits that leverage this principle to perform logic, arithmetic and complex vector operations. We address the challenge of reliable in-memory computing under process variations by extending ECC schemes to detect and correct errors that occur during CiM operations. We also address the question of how STT-CiM should be integrated within a generalpurpose computing system. To this end, we propose architectural enhancements to processor instruction sets and on-chip buses that enable STT-CiM to be utilized as a scratchpad memory. Finally, we present data mapping techniques to increase the effectiveness of STT-CiM. We evaluate STT-CiM using a device-to-architecture modeling framework, and integrate cycle-accurate models of STT-CiM with a commercial processor and on-chip bus (Nios II and Avalon from Intel). Our system-level evaluation shows that STT-CiM provides system-level performance improvements of 3.93x on average (upto 10.4x), and concurrently reduces memory system energy by 3.83x on average (upto 12.4x).

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“…The emergence of the RRAM as a NVM device which can compute, at a time when computer architects are facing the memory wall problem, has set the stage for RRAM to be efficiently deployed for in-memory computing. A new field called 'memristive logic' [1] has emerged, which is the methodology of designing logic circuits using RRAM as the primary computing device. Consequently, research in RRAM-based memories [2] and RRAM-based computing circuits [3] are very active and ever increasing.…”

Section: Introductionmentioning

confidence: 99%

A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability

Reuben

Fey

Wenger

2019

IEEE Trans. Nanotechnology

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Modeling of Resistive RAMs (RRAMs) is a herculean task due to its non-linearity. While the exigent need for a model has motivated research groups to formulate realistic models, the diversity in RRAMs' characteristics has created a gap between model developers and model users. This paper bridges the gap by proposing an algorithm by which the parameters of a model are tuned to specific RRAMs. To this end, a physicsbased compact model was chosen due to its flexibility, and the proposed algorithm was used to exactly fit the model to different RRAMs, which differed greatly in their material composition and switching behavior. Further, the model was extended to simulate multiple Low Resistance States (LRS), which is a vital focus of research to increase memory density in RRAMs. The ability of the model to simulate the switching from a high resistance state to multiple LRS was verified by measurements on 1T-1R cells.

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Memristive logic: A framework for evaluation and comparison

Cited by 81 publications

References 23 publications

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Memristive Logic in Crossbar Memory Arrays: Variability-Aware Design for Higher Reliability

Computing in Memory With Spin-Transfer Torque Magnetic RAM

A Modeling Methodology for Resistive RAM Based on Stanford-PKU Model With Extended Multilevel Capability

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