Memristor‐Based Analog Computation and Neural Network Classification with a Dot Product Engine

Hu, Miao; Graves, Catherine E.; Li, Can; Li, Yuning; Ge, Ning; Montgomery, Eric; Dávila, Noraica; Jiang, Hao; Williams, R. Stanley; Yang, J. Joshua; Xia, Qiangfei; Strachan, John Paul

doi:10.1002/adma.201705914

Cited by 625 publications

(484 citation statements)

References 57 publications

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“…Most electrical characterization was carried out using our custom-built multiboard measurement system 51 . A photograph and description of the system are provided in Supplementary Fig.…”

Section: Nature Electronicsmentioning

confidence: 99%

Analogue signal and image processing with large memristor crossbars

et al. 2017

Nat Electron

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“…Most electrical characterization was carried out using our custom-built multiboard measurement system 51 . A photograph and description of the system are provided in Supplementary Fig.…”

Section: Nature Electronicsmentioning

confidence: 99%

Analogue signal and image processing with large memristor crossbars

et al. 2017

Nat Electron

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“…[6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy.…”

mentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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in computing accelerators compared to high density storage-class memory, it is frequently important in computing applications to program multiple bits of information within every device by achieving many distinct conductance levels, while keeping the operating currents lower especially at the high conductance states. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy. For example, in analog matrix-vector multiplication, voltage drops across metal interconnect lines cause computational errors and, therefore, the memristor array size must be limited. [6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. This further benefits the energy and area efficiency by amortizing the costs of anolog to digital converters (ADC) required in the circuit. [4] However, existing demonstrations have a narrow dynamic range and achieving multiple low conductance levels is challenging. A larger ratio between the high and low conductances (on/off ratio) helps in achieving more distinct programmable low conductance levels. In addition, memristors are required to be integrated with CMOS circuits in many such applications. For instance, a 1-transistor-1-memristor (1T1M) combination provides in situ current compliance through gate voltage modulation so that the memristor can be programmed in an analog manner. [12,16,25] This brings another challenge: compatibility of memristor and CMOS. This includes not only material and fabrication compatibility, but also CMOS performance meeting the memristor operating requirements as both continue size scaling. Thus, it is essential to demonstrate all the aforementioned properties in nanometer-scale memristors repeatedly and reproducibly.Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.Using memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. Such accelerators have demonstrated the potential to significantly outperform digital computers in highly relevant applications such as machine learning and image processing. However, improvements in device-level performance of memristors, including reducing power consumption and high current-induced metal migration in interconnects, need continued developments. Nanoscaling and complementary metal-oxide semiconductor (CMOS) integration are also of significant ...

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“…To be more specific, RRAM devices enable logicin-memory to perform stateful logic operations. [61] In the analog scheme, the synaptic weights directly map as the conductance values. [50] A large-scale array of stateful logical RRAM is the aggregation of these basic logic gates similar to the transistor-based arithmetic units.…”

Section: Rram Basics and Rram Array For Inferencementioning

confidence: 99%

“…[61] The digital inputs vectors are converted into queues of analog voltages, and DPE performs computation. RRAM-based in-memory computing indeed operates in an analog format and requires data conversion for such a macro to interface with its surrounding digital systems.…”

Section: Analog/digital Converter-based Designmentioning

confidence: 99%

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Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

Yan

Qiao

et al. 2019

Advanced Intelligent Systems

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In‐memory computing is a computing scheme that integrates data storage and arithmetic computation functions. Resistive random access memory (RRAM) arrays with innovative peripheral circuitry provide the capability of performing vector‐matrix multiplication beyond the basic Boolean logic. With such a memory–computation duality, RRAM‐based in‐memory computing enables an efficient hardware solution for matrix‐multiplication‐dependent neural networks and related applications. Herein, the recent development of RRAM nanoscale devices and the parallel progress on circuit and microarchitecture layers are discussed. Well suited for analog synapse and neuron implementation, RRAM device properties and characteristics are emphasized herein. 3D‐stackable RRAM and on‐chip training are introduced in large‐scale integration. The circuit design and system organization of RRAM‐based in‐memory computing are essential to breaking the von Neumann bottleneck. These outcomes illuminate the way for the large‐scale implementation of ultra‐low‐power and dense neural network accelerators.

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Memristor‐Based Analog Computation and Neural Network Classification with a Dot Product Engine

Cited by 625 publications

References 57 publications

Analogue signal and image processing with large memristor crossbars

Analogue signal and image processing with large memristor crossbars

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

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