Memristors' Potential for Multi-bit Storage and Pattern Learning

TaheriNejad, Nima; Manoj, P K; Jantsch, Axel

doi:10.1109/ems.2015.73

Cited by 14 publications

(1 citation statement)

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“…A signiicant portion of the total processing time and the total energy consumption is wasted on 1) reading the data from memory, 2) transferring the data between memory and processing unit, and 3) writing the result back into the memory [7] [30] [53] [32] [63]. In-Memory Computation (IMC) or Processing in Memory (PIM) is an emerging computational approach that ofers the ability to both store and process data within memory cells [5,26,27,52,60,62,66,69]. This technique eliminates the high overhead of transferring data between memory and processing unit, improving the performance and reducing the energy consumption by processing data in memory.…”

Section: Introductionmentioning

confidence: 99%

Sorting in Memristive Memory

Alam

Najafi

TaheriNejad

2022

J. Emerg. Technol. Comput. Syst.

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Sorting data is needed in many application domains. Traditionally, the data is read from memory and sent to a general-purpose processor or application-specific hardware for sorting. The sorted data is then written back to the memory. Reading/writing data from/to memory and transferring data between memory and processing unit incur significant latency and energy overhead. In this work, we develop the first architectures for in-memory sorting of data to the best of our knowledge. We propose two architectures. The first architecture is applicable to the conventional format of representing data, i.e., weighted binary radix. The second architecture is proposed for developing unary processing systems, where data is encoded as uniform unary bit-streams. As we present, each of the two architectures has different advantages and disadvantages, making one or the other more suitable for a specific application. However, the common property of both is a significant reduction in the processing time compared to prior sorting designs. Our evaluations show on average 37 × and 138 × energy reduction for binary and unary designs, respectively, compared to conventional CMOS off-memory sorting systems in a 45nm technology. We designed a 3 × 3 and a 5 × 5 Median filter using the proposed sorting solutions, which we used for processing 64 × 64 pixel images. Our results show a reduction of 14 × and 634 × in energy and latency, respectively, with the proposed binary, and 5.6 × and 152 × 10 3 in energy and latency with the proposed unary approach compared to those of the off-memory binary and unary designs for the 3 × 3 Median filtering system.

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