Abstract:Defining padring and its pad interconnections is one of the most time consuming steps of a microcontroller SoC design. Also, multiple device features plus testability in limited pinout packages entails more functions shared per pin. As such, the number of padring connections and complexity exponentially grows at each new design. This paper describes a methodology to configure pad connections and select correct pad cells. The methodology works out technology and function definitions for each pin using new and p… Show more
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