Method for reducing of noise by improving signal-to-noise-ratio in wireless LAN

Seshadri, Ravi; Penchalaiah, N.

doi:10.48550/arxiv.1110.2267

2011

DOI: 10.48550/arxiv.1110.2267

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Method for reducing of noise by improving signal-to-noise-ratio in wireless LAN

Ravi Seshadri¹,

N. Penchalaiah²

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2018

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Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

et al. 2018

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Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

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Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

et al. 2018

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Method for reducing of noise by improving signal-to-noise-ratio in wireless LAN

Cited by 1 publication

References 3 publications

Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

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