Methods for fault tolerance in networks-on-chip

Radetzki, Marian; Cao, Feng; Zhao, Xueqian; Jantsch, Axel

doi:10.1145/2522968.2522976

Cited by 175 publications

(90 citation statements)

References 102 publications

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“…Assuming a transient fault on the "victim" region of segment S i could deadlock the pipeline, the input active wire and the ack wire to the pre-fault stage Stage i, (A i , ack i+1 ), should get stuck at either (11) or (00) to avoid any state transitions according to the deadlock definition. a) (A i , ack i+1 ) gets stuck at (11).…”

Section: B Deadlock Caused By Transient Faultsmentioning

confidence: 99%

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Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults

Zhang

Garside

Song

et al. 2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

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Abstract-Asynchronous Networks-on-Chip (NoCs) have been proposed as a promising infrastructure to provide scalable and efficient on-chip communication for many-core systems. Using the Quasi-delay-insensitive (QDI) implementation, asynchronous NoCs could achieve timing-robustness. However, the advancing semiconductor technology leads to shrinking transistor dimensions and increasing chip density, accelerating the occurrence of faults, especially transient faults. Transient faults emerging on QDI circuits could cause not only data errors (symbol corruption and insertion), but also deadlock. When the deadlock happens on asynchronous NoCs, it can spread over the whole network and paralyse its function. This deadlock has not been fully studied while most traditional fault-tolerant techniques cannot deal with it. Using a new model built for QDI pipelines, the formation and behaviour of the deadlock caused by transient faults are systematically studied. Using the summarized deadlock patterns, the fault position can be precisely located and the fault type can be diagnosed. A fine-grained recovery mechanism is proposed to recover the network from different deadlocks. As a design case, an asynchronous NoC is designed which can recover from the deadlock caused by both transient and permanent faults on links. Detailed experimental results are given.

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Section: B Deadlock Caused By Transient Faultsmentioning

confidence: 99%

“…It could spread over the whole asynchronous NoC and paralyse its function. The error detection and correction on synchronous NoCs have been fully studied [11] pipelines and the effect of transient faults. Using this pipeline model, the formation and behaviour of the deadlock caused by transient faults are systematically studied.…”

Section: Introductionmentioning

confidence: 99%

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults

Zhang

Garside

Song

et al. 2015

2015 21st IEEE International Symposium on Asynchronous Circuits and Systems

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“…In order to improve the robustness of network, fault-tolerant strategies are employed to struggle against the attacks in both the physical and logical layers of the communication network [7,8].The analysis and estimation of robustness can avoid suffering, lower the risk, and help to improve the reliability [9,10].…”

Section: Introductionmentioning

confidence: 99%

A Communication Network Robustness Estimation Method Based on an Improved ELM

Wen¹,

Huang²,

Wu³

2017

dtcse

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Abstract. The communication network robustness is becoming increasingly important because of its wider applications on higher reliability requirement systems, such as UAV, CBTC, etc. But communication network robustness estimation is becoming more difficult due to related various factors such as attacks, EMI, errors, mobility, fault-tolerant strategies, etc. With the purpose of estimating the robustness of communication network, most existing network robustness estimation researches mainly focus on failures in network physical layer and take complex network methods to estimate network robustness; recently, others have used Monte Carlo method to consider nodes mobility and several researches have summed up whole factors with weights to estimate the network robustness by AHP methods. Though these methods have largely been exploited to estimate the robustness of networks approximately, there is still no proper method to estimate the robustness of real communication network with consideration of nonlinear relationships among multiple factors. In this study, firstly, a double-layer network robustness model has been constructed; secondly, in order to take more robustness related factors into consideration, we have constructed a simulation platform based on NS-3; finally, wehave proposed a novel robustness estimation method based on improved ELM (extreme learning machine), which is powerful to estimate the nonlinear relationships. The novel robustness estimation method has been formed by four steps: simulation and data collection, improved EML, model training, and estimation. In the end, contrast analyzes have been made to illustrate three facts: (1) fault-tolerant strategies can improve the robustness obviously;(2) our double-layer network robustness model is better than the previous model; (3) the improved ELM has a better cross-validation accuracy which is above 95%.

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“…Permanent faults are due to two major effects: The increasing complexity of chip manufacturing gives rise to higher rates of post manufacturing defects caused by inaccuracies of the photolithographic and etching processes, leading to variability of material impurities, doping concentrations and size, and geometries of structures 1 . On the other hand, decreasing feature sizes cause faster transistor aging and eventually transistor wear out, caused by Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), Electro-migration, and Time Dependent Dielectric Breakdown (TDDB) [1].On another side, soft errors are apt to occur at any time during the normal 1 International Roadmap Committee.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, decreasing feature sizes cause faster transistor aging and eventually transistor wear out, caused by Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), Electro-migration, and Time Dependent Dielectric Breakdown (TDDB) [1].On another side, soft errors are apt to occur at any time during the normal 1 International Roadmap Committee. 2014. www.itrs.net operation states of the system and affect randomly any part of the system.…”

Section: Introductionmentioning

confidence: 99%

Collaborative Routing Algorithm for Fault Tolerance in Network on Chip CRAFT NoC

Nehnouh¹,

Senouci²,

Chaib³

2017

ijacsa

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Abstract-Many fault tolerance techniques have been proposed in Network on Chip to cope with defects during fabrication or faults during product lifetime. Fault tolerance routing algorithm provide reliable mechanisms for continue delivering their services in spite of defective nodes due to the presence of permanent and/or transient faults throughout their lifetime implementation. This paper presents a new approach in the domain of fault-tolerant NoC with two main contributions. Firstly, we consider a unified fault model that include transient faults, permanent faults and congestion considered as a fault. Secondly, we present a new architecture based on sub-nets and give an overview of the associated test and (re)routing algorithm. The main result of this paper, is a new routing algorithm called Collaborative Routing Algorithm for Fault Tolerance in Network on Chip (CRAFT-NoC). We compare our approach with ACO-FAR that considers as well congestion and permanent faults. Our simulation results show significant improvements in terms of both latency and reliability.

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Methods for fault tolerance in networks-on-chip

Cited by 175 publications

References 102 publications

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults

Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults

A Communication Network Robustness Estimation Method Based on an Improved ELM

Collaborative Routing Algorithm for Fault Tolerance in Network on Chip CRAFT NoC

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