Microstructure and Granularity Effects in Electromigration

Abstract

The persistent advancements made in the scaling and vertical implementation of front-end-of-line transistors has reached a point where the back-end-of-line metallization has become the bottleneck to circuit speed and performance. The continued scaling of metal interconnects at the nanometer scale has shown that their behavior is far from that expected from bulk films, primarily due to the increased influence that the microstructure and granularity plays on the conductive and electromigration behavior. The impact of microstructure is noted by a sharp shift in the changing crystal orientation at the grain boundaries and the roughness introduced at the interfaces between metal films and the surrounding dielectric or insulating layers. These locations are primary scattering centers of conducting electrons, impacting a film's electrical conductivity, but they also impact the diffusion of atoms through the film during electromigration. Therefore, being able to fully understand and model the impact of the microstructure on these phenomena has become increasingly important and challenging, because the boundaries and interfaces must be treated independently from the grain bulk, where continuum simulations become insufficient. In light of this, recent advances in modeling electromigration in nanometer sized copper interconnects are described, which use spatial material parameters to identify the locations of the grain boundaries and material interfaces. This method reproduces the vacancy concentration in thin copper interconnects, while allowing to study the impact of grain size and microstructure on copper interconnect lifetimes.

Enhancement of Electromigration Reliability of Electroless-Plated Nanoscaled Copper Interconnects by Complete Encapsulation of a 1 nm-Thin Self-Assembled Monolayer

“…Indeed, the high activation energy of 0.93 eV for the SAM-fully-passivated Cu interconnects suggests that their failure is primarily through EMinduced diffusion of Cu via either grain boundaries or grains. 28,33 As noted in Fig. 6, activation energies of both Cu(SAM) and Cu lines are gradually increased with annealing temperature.…”

“…Previous EM studies have suggested that relatively low activation energy values ranging from 0.50 to 0.65 eV are typical of Cu interconnects involving interface/surface diffusion. 29,32,33 Using a bamboo-like microstructure or a capping layer to block the fastest (interfacial/surface) diffusion routes further strengthens EM reliability of Cu interconnects and elevates the activation energies to typically 0.7-0.8 eV, characteristics of grain-boundary diffusion. 28,33,34 Moreover, adhesion is regarded as another important factor that decides the reliability of a metal interconnect line under EM testing.…”

“…29,32,33 Using a bamboo-like microstructure or a capping layer to block the fastest (interfacial/surface) diffusion routes further strengthens EM reliability of Cu interconnects and elevates the activation energies to typically 0.7-0.8 eV, characteristics of grain-boundary diffusion. 28,33,34 Moreover, adhesion is regarded as another important factor that decides the reliability of a metal interconnect line under EM testing. A weakened adhesion renders the deposited Cu to debond from a substrate, and accelerates Cu diffusion via free surface or substrate interface, also giving reduced values of activation energy for EM.…”

“…As is well-known, EM reliability of a metal interconnect is influenced by its microstructure. Adequate annealing increases the crystallinity of copper grains 33,38 or densifying Cu grain boundaries 28 that substantially extends the EM lifetime of the Cu interconnects. Increasing the adhesion strength of Cu by annealing is also important for the reliability enhancement of the interconnects.…”

Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices

“…This intricate network of components, Since interconnects ultimately serve as pathways for current transmission, it is necessary to minimize the heat generated by Joule heating resulting from current flow [11]. However, in situations requiring scaling down, the shrinking size of vias gradually has become a cause of current flow bottlenecks within the metal line, making them susceptible to Joule heating [12,13]. Therefore, this study utilized the finite element method (FEM) technique [14,15] to model interconnects in a simplified structure and conducted simulations to analyze the extent to which Joule heating, based on the area ratio between the metal line and via, affects the reliability of the interconnect.…”