Mismatch error shaping of DAC unit elements in multibit ∆Σ modulators using a novel unified ADC/DAC

Abstract

This paper presents a unified analog to digital converter (ADC) and digital to analog converter (DAC) for multi-bit ∆Σ modulators. The unified ADC/DAC circuit provides error shaping for mismatches between DAC unit elements. Hence, the dynamic element matching (DEM) circuit or digital calibration is not required resulting in the area and power saving as well as the elimination of the excess loop delay introduced by DEM circuit. Incorporating a 6-bit unified ADC/DAC, the ∆Σ modulator achieves 16.15-bit resolution utilizing only a second order loop filter and oversampling ratio of 40. The proposed modulator is simulated in a 65-nm CMOS process. Intended for audio applications, it achieves 102-dB dynamic range, and 99-dB signal to noise and distortion ratio in a 25-kHz bandwidth sampled at 2 MS/s. The power dissipation and power supply are 149.8 µ W and 1.4 V, respectively.