Mitigating the Effect of Multiple Event Upsets in FPGA-Based Automotive Applications

Shaker, Manar N.; Hussien, Ahmed; Alkady, Gehad I.; Amer, Hassanein H.; Adly, Ihab

doi:10.1109/meco.2019.8760189

Cited by 5 publications

(7 citation statements)

References 12 publications

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“…The hexa modular redundancy (6MR) fault-tolerant technique [7,10] can detect this specific sequence, as well as additional failure sequences. 6MR follows the same methodology as TMR and 5MR.…”

Section: Methodsmentioning

confidence: 99%

“…The failed modules can be recovered using DPR. In [7], it was proven that 6MR was more reliable than 5MR, with λs (SEU rate) 10 times higher than λ d (DEU rate) based on the data in [3,15]. The reliability was calculated by simulating Markov models for 5MR and 6MR using SHARPE [16].…”

Section: Methodsmentioning

confidence: 99%

“…As mentioned in this section, for the 5MR system, five identical copies of the module (M) are connected to a voter (an error detection and recovery mechanism). 5MR can tolerate 3 successive single failures in 3 different Ms or a double failure in two Ms followed by a single failure in a third M. DPR is used to recover the failed modules [7]. For the Markov model in Figure 2, the state is named according to the number of operating modules in this state and "F" is the failure state.…”

Section: Effect Of Failure Rates Ratio On Reliabilitymentioning

confidence: 99%

“…Failures and repair times are both assumed to be exponentially distributed; hence, the repair rate µ and the failure rate λ are constant [10]. In [7], it was proven that 6MR was more reliable than 5MR, with λs (SEU rate) 10 times higher than λd (DEU rate) based on the data in [3,15]. The reliability was calculated by simulating Markov models for 5MR and 6MR using SHARPE [16].…”

Section: Effect Of Failure Rates Ratio On Reliabilitymentioning

confidence: 99%

“…In [7], many fault tolerance techniques were studied to mitigate SEUs and MEUs (especially non-adjacent double event upsets (DEUs)). The first technique is scrubbing; it requires a time interval (this time interval can be in order of milliseconds) between the occurrence of the error in the configuration memory of the FPGA and the time to discover and repair this error [8].…”

Section: Introductionmentioning

confidence: 99%

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FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

et al. 2020

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Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well as DPR to mitigate SEUs and MEUs. Then, it is implemented on Xilinx Vivado tools targeting the Kintex7 7k410tfbg676 device. Finally, we show how to render this design fault secure in the event that SEUs or MEUs affect the voter itself. This fault secure voter either produces the correct output or gives an indication that the output is incorrect.

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Section: Methodsmentioning

confidence: 99%