Modeling and Analysis of the Effects of PCB Parasitics on Integrated DC-DC Converters

Abstract

Load transients are prevalent in every electronic device including semiconductor memory, card readers, microprocessors, disc drives, piezoelectric devices, and digitally based systems. They are capable of producing voltage stress, introducing noise, and degrading device functionality. In order to avoid damage to the device, a feedback control loop is implemented with system compensation to regulate the output voltage deviations by the converter. Because designing compensation networks can be rather complicated, DC-DC converters with integrated feedback control topologies help minimize design time and complexity of converter compensation at the expense of design flexibility. This thesis widens the limitations of an integrated DC-DC converter with a stability optimization technique that utilizes the feedback network to create a phase boost centered at the bandwidth of the converter to increase the phase margin and improve its transient response. Ideal modeling verifies stability optimization while non-ideal modeling that introduces PCB parasitics to the control loop suggest an additional phase boost in the feedback network. Experimental data confirms this non-deal model for parasitic capacitances higher than calculated. The modified non-ideal model shows more accuracy compared to the experimental data which indicates that there may be PCB parasitics that is unaccounted for. Modeling the modified non-ideal model to high orders may yield more accuracy. This thesis gives both DC-DC converter and PCB layout designers insight and considerations into PCB effects on the stability of DC-DC converters and the optimization of integrated compensation.