Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets

Blume, Holger; Sydow, T. von; Becker, Daniel; Noll, Tobias G.

doi:10.1007/11512622_40

Cited by 2 publications

(1 citation statement)

References 6 publications

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“…Authors in [26] applied deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication. In their contribution, the modeling of basic NOC communication scenarios featuring different processor cores, network topologies and communication schemes is presented.…”

Section: Petri Nets and Their Extensionsmentioning

confidence: 99%

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Boutekkouk

2018

Int. J. Recent Contrib. Eng. Sci. IT

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Network-On-Chip (NOC) is an emerging paradigm to surmount traditional bus based Systems-On-Chip (SOC) limits especially scalability and communication performances. A NOC includes many applications that can execute concurrently. This situation may show some undesirable behaviors such as deadlock, livelock, starvation, etc. On the other hand, the application of formal methods to on-chip communication infrastructures has recieved more attention. Formal analysis of NOC communication will be very advantageous since it allows proving some theorems or interesting qualitative/quantitative properties on the communication behavior where simulation/emulation techniques can fail easily. In this paper we try to giva an overview of the most famous formal methods applied to the verification of communication inside NOCs.

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Section: Petri Nets and Their Extensionsmentioning

confidence: 99%

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Boutekkouk

2018

Int. J. Recent Contrib. Eng. Sci. IT

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Modeling networking issues of network-on-chip: a coloured petri nets approach

Bazzaz

Sirjani

Khosravi

et al. 2009

Proceedings of the Second International ICST Conference on Simulation Tools and Techniques

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Network-on-Chip (NoC) is proposed as a new scalable architecture to address the future design challenges of system-ona-chip (SoC). As current verification techniques for on-chip communication algorithms are typically complicated tasks including many hardware modules and software routines, verifying the algorithms themselves is almost impossible. Having the incentive for simplifying verification of these on-chip algorithms, in this paper, we propose a detailed NoC CPN model in which key NoC networking challenges, namely network topology, switching method, and routing algorithm are considered. By this model, any desired NoC topologies, including but not limited to, mesh and k-ary ncube can be constructed. As for switching techniques, dominant on-chip switching methods, namely, packet switching, circuit switching, and wormhole switching, are modeled. Besides, as model of a NoC switch element is highly dependent on its switch fabric type, different sorts of switching fabrics, i.e., crossbar and shared bus, are modeled in this contribution. For routing the packets between cores, a CPN version of dimension-ordered routing, dominant routing algorithm for NoC, is implemented in the switches.

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Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets

Cited by 2 publications

References 6 publications

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Modeling networking issues of network-on-chip: a coloured petri nets approach

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