Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance

Choi, Chang-Hoon; Dutton, R.W.

doi:10.1006/spmi.1999.0799

Cited by 10 publications

(4 citation statements)

References 12 publications

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“…One solution to this lack of quantum potential BCs is to solve the DGET model in the oxide as well as in the adjoining silicon and poly gate. This will allow us to simulate the tunneling effects across the oxide [13]. This issue is not addressed here and will be reported elsewhere in our future works.…”

Section: Numerical Examplesmentioning

confidence: 94%

A quantum corrected energy-transport model for nanoscale semiconductor devices

Chen¹,

Liu²

2005

Journal of Computational Physics

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Section: Numerical Examplesmentioning

confidence: 94%

A quantum corrected energy-transport model for nanoscale semiconductor devices

Chen¹,

Liu²

2005

Journal of Computational Physics

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“…Secondly, since the charge is dependent on the amount of the bandgap increase, the gate capacitance, which is the derivative of the channel charge with respect to the gate bias, will suffer from singularity at flatband condition. [43] To overcome the drawbacks of these models, a hybrid model [44,45] is proposed in which the effective density of states is a function of distance from the surface while maintaining the bandgap in the surface region as a function of surface transverse electric field. To eliminate the flatband singularity of evaluating the capacitance, the E s 2 3 term in eqn.…”

Section: Widening Of the Band-gap And Modification Of Intrinsic Carrimentioning

confidence: 99%

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

Srikantaiah

DasGupta

2012

IETE Tech Rev

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In this paper, the quantum mechanical (QM) effects in bulk MOSFETs and their modeling approaches in the compact modeling framework are reviewed. As the device dimensions are scaled to the sub-100 nm range, QM effects affect the device properties, such as effective oxide thickness, inversion layer charge density and profile, threshold voltage, effective bandgap, gate capacitance, mobility, surface potential, subthreshold characteristics, drain current, and gate leakage current. The classical theory is no longer sufficient for accurate modeling of these device characteristics. In this paper, models which have incorporated QM effects to obtain the device characteristics are discussed and compared. The roles of QM effects in affecting some of the device properties are also presented. KeywordsBulk MOSFETs, Quantum mechanical effect, Review on compact modeling. ( ) , which is used to solve eqn. (1) by numerical methods. Only certain energy levels, denoted by E ij , satisfy the Schrödinger equation and correspond to the energy levels of the sub-bands. Here, i=L for the lower valley and i=H for the higher valley, while j=0, 1, 2, 3…, corresponds the sub-band number. The electron concentration n y IETE TECHNICAL REVIEW | VOL 29 | ISSUE 1 | JAN-FEB 2012 AUTHORS Jayadeva Gowrapura Srikantaiah received the B.E. degree in electronics and communication engineering from NMAM Institute of Technology, Nitte, in 1990, M.Tech degree in digital electronics and advanced communication from the Karnataka Regional Engineering College, Surathkal (Present NITK), in 1995, both were affiliated to Mangalore University, India and Ph.D degree from I.I.T. Madras in 2010. His Ph.D. dissertation was on analytical models incorporating quantum mechanical effects for short n-channel MOSFETS. He joined as a lecturer in NMAM Institute of Technology, Nitte, in 1990 and later as Assistant Professor at JNNCE Shimoga in 1998. He has been a Faculty member in the department of electronics and communication engineering, Nagarjuna College of Engineering and Technology, Bangalore, since September 2010 and is currently a Professor and Head. His research interests are modeling and simulation of bulk and SOI MOSFETs including quantum mechanical effects and low power VLSI design.

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“…This field distorts the silicon bandgap, such that electrons may more easily travel from the valence to the conduction band, from the gate to the channel and body. The following models for direct tunneling current may be used to better understand this leakage component [7]:…”

Section: Introductionmentioning

confidence: 99%

Design limitations in deep sub-0.1μm CMOS SRAM

Grube

Wang

Kang

2002

Proceedings of the 12th ACM Great Lakes Symposium on VLSI

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Leakage effects in deep sub-0.1µm CMOS technologies are of critical concern to designers of high-performance integrated circuits. Recent estimates [1] of a 7.5x increase in leakage current per chip generation; along with several proposals for energyefficient cache architectures that unfortunately do not address static leakage-energy issues [2], [3], [4], have heightened concerns over the functionality and stability of future high-performance SRAM cache designs.Each of these future technology generations, in addition to having increased short-channel effects (SCEs) will now also suffer from gate leakage currents across physically and electrically thin (~1.5nm) SiO 2 gate dielectrics. In this paper we demonstrate the limits of this scaling on the operational behavior of on-chip SRAM cache designs, and briefly discuss the impact of these results on high-performance memory architectures.

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Modeling of MOS scaling with emphasis on gate tunneling and source/drain resistance

Cited by 10 publications

References 12 publications

A quantum corrected energy-transport model for nanoscale semiconductor devices

A quantum corrected energy-transport model for nanoscale semiconductor devices

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

Design limitations in deep sub-0.1μm CMOS SRAM

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