Modeling of the SiO<sub>2</sub>/SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

Licciardo, Gian Domenico; Benedetto, Luigi Di; Bellone, Salvatore

doi:10.1109/ted.2016.2531796

Cited by 37 publications

(12 citation statements)

References 21 publications

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“…The gate oxide thickness is set to 30 nm and the device width is 10 cm [2,15]. The donor concentration of n-epi region which has been used in the simulation is N D =3×10 15 cm −3 [2,15,16]. In addition, figure 1 shows also the relevant resistances affecting the carrier transport and its related locations.…”

Section: Device Structure Measurements and Simulation Methodologymentioning

confidence: 99%

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

et al. 2020

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Section: Device Structure Measurements and Simulation Methodologymentioning

confidence: 99%

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

et al. 2020

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“…1. The donor concentration of p‐epi region is

N_{D} = 3 \times 10^{15} c {normalm}^{- 3}

, while the acceptor concentration (p‐type region) is given by a Gaussian profile with a maximum doping concentration of

N_{A} = 5 \times 10^{16} c {normalm}^{- 3}

and a decay (standard deviation) of 3 μm in the x ‐direction and of 4.5 μm in the y ‐direction like in [5, 26]. The gate oxide thickness was set to 30 nm and the MOS channel length, which is defined by the distance between the edges of n + source regions and the P‐wells, is 6 μm and the device width is 10 cm [5].…”

Section: Methodsmentioning

confidence: 99%

Impact of interface traps/defects and self‐heating on the degradation of performance of a 4H‐SiC VDMOSFET

Alqaysi

Martı́nez

Ahmeda

et al. 2019

IET Power Electronics

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The reliability of silicon carbide metal oxide semiconductor field-effect transistors remains a challenge in power applications and relates to the SiO 2-SiC interface. The presence of unwanted interface traps/defects degrades the device performance. The impact of acceptor traps/defects on the performance of a 4H-SiC vertical Diffused Metal Oxide Semiconductor Field Effect Transistor (DMOSFET) with a breakdown voltage of 1700 V is investigated.-and-characteristics were simulated, using a drift-diffusion model coupled to Fourier heat equations, and are in a good agreement with experimental results. The presence of interface traps/defects were shown to produce degradation of threshold voltage, but the impact diminishes as temperature increases. A threshold voltage shift of 3.5 V occurs for a trap concentration of 2 × 10 13 cm-2 /eV at room temperature. The transfer characteristics obtained from electro-thermal modelling show a larger degradation than those at a constant temperature. This degradation increases with the drain bias increase. The threshold voltage from the electro-thermal simulations is 5 V compared to 4 V observed in constant 423 K temperature simulations at. Finally, the interface traps/defects increases breakdown voltage exhibiting a strong dependency on the trap density and their energy decay characteristics.

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“…The dimensions and material properties are obtained according to the published article [4]. The dimension and doping concentration of the embedded p-layer, which are not described in [4], are determined referring to [10][11][12][13]. Current flows upwards, from the bottom (drain) to top (source), in the figure.…”

Section: Tcad Simulationmentioning

confidence: 99%

Modeling of interelectrode parasitic elements of V-groove SiC MOSFET

Zhou

Shintani

Hiromoto

et al. 2018

NOLTA

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We propose a physics-based model of interelectrode parasitic elements of a Vgroove SiC power MOSFET with buried players. The proposed model considers the voltage dependence of parasitic resistances and capacitances on the basis of the observations through technology computer aided design (TCAD) simulations. The gate-voltage dependence of the body diode is also modeled in accordance with device physics. Through comparison with measurement results, it is demonstrated that the proposed model successfully reproduces both I-V and C-V characteristics. The transient behavior using a buck converter is also well reproduced.

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Modeling of the SiO₂/SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

Cited by 37 publications

References 21 publications

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

Impact of interface traps/defects and self‐heating on the degradation of performance of a 4H‐SiC VDMOSFET

Modeling of interelectrode parasitic elements of V-groove SiC MOSFET

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Modeling of the SiO2/SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET

Cited by 37 publications

References 21 publications

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

Influence of temperature and dimension in a 4H-SiC vertical power MOSFET

Impact of interface traps/defects and self‐heating on the degradation of performance of a 4H‐SiC VDMOSFET

Modeling of interelectrode parasitic elements of V-groove SiC MOSFET

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Modeling of the SiO₂/SiC Interface-Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET