Modeling resource sharing using FSM-SADF

Bastos, João; Stuijk, Sander; Voeten, J.P.M.; Schiffelers, R.R.H.; Jacobs, Johan; Corporaal, Henk

doi:10.1109/memcod.2015.7340475

Cited by 4 publications

(2 citation statements)

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“…Utilizing purely analytical approaches to obtain upper and lower timing bound of dataflow applications execution time is a wide spread research topic. Closest to our research are [12,9,11,2]. While such approaches are fast and able to handle large systems, unfortunately they deliver pessimistic results especially when handling state-based bus arbitration protocols typically used in Multi-Processor Systems on a Chip (MPSoCs).…”

Section: Related Workmentioning

confidence: 99%

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Stemmer

Fakih

Grüttner

et al. 2017

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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CITATIONS 0 READS 22 4 authors, including: Some of the authors of this publication are also working on these related projects: 3Ccar -Integrated Components for Complexity Control in affordable electrified cars View project SAFEPOWER -Safe and secure mixed-criticality systems with low power requirements View project Maher Fakih OFFIS e.V. ABSTRACTScenario-Aware Data-Flow Graphs (SADFGs) were introduced to capture the behavior of embedded applications achieving a good trade-off between expressiveness and analyzability. On the one side, they support the timing analysis of real-time applications, especially those running on MPSoCs, due to the clean separation of computation and communication phases in their executing nodes. On the other side, SADFGs allow the expression of a more dynamic behaviors than Synchronous dataflow graphs by allowing dynamic token-rates of single nodes depending on pre-defined typical scenarios. The fact which leads to more efficiency and better throughput.In this paper, we describe the extension of a previous model-checking based real-time analysis approach to allow the analysis of timing bounds for FSM-SADFGs mapped on a shared memory multiprocessor architecture. We demonstrate our approach on an MPEG decoder application being viable to obtain the worst-case end-to-end latency of its implementation under different scenarios on a 2-tiles MPSoC.

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Section: Related Workmentioning

confidence: 99%

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Stemmer

Fakih

Grüttner

et al. 2017

Proceedings of the 9th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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“…It is possible to convert a model in our formalism to an FSM-SADF model. As studied in [13], each activity can be mapped onto an SDF scenario, and the Activity-FSM corresponds to the FSM in FSM-SADF. Note that an SDF scenario is more general, since it can also contain cycles.…”

Section: Related Workmentioning

confidence: 99%

Compositional specification of functionality and timing of manufacturing systems

Sanden

Bastos

Voeten

et al. 2016

2016 Forum on Specification and Design Languages (FDL)

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van der Sanden, L.J.; Nogueira Bastos, J.P.; Voeten, J.P.M.; Geilen, M.C.W.; Reniers, M.A.; Basten, T.; Jacobs, J.; Schiffelers, R.R.H. Published in:Proceedings of the 2016 Forum on specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016 Published: 01/09/2016 Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA):van der Sanden, L. J., Nogueira Bastos, J. P., Voeten, J. P. M., Geilen, M. C. W., Reniers, M. A., Basten, T., ... Schiffelers, R. R. H. (2016). Compositional specification of functionality and timing of manufacturing systems. In Proceedings of the 2016 Forum on specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016 General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-This paper introduces a formal modeling approach for compositional specification of both functionality and timing of manufacturing systems. Functionality aspects can be considered orthogonally to timing aspects. The functional aspects are specified using two abstraction levels; high-level activities and lower level actions. Design of a functionally correct controller is possible by looking only at the activity level, abstracting from the different execution orders of actions and their timing. As a result, controller design can be performed on a much smaller state space compared to an explicit model where timing and actions are present. The performance of the controller can be analyzed and optimized by taking into account the timing characteristics. Since formal semantics are given in terms of a (max, +) sta...

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Modeling resource sharing using FSM-SADF

Bastos

Stuijk

Voeten

et al. 2015

2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)

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Abstract-This paper proposes a modeling approach to capture the mapping of an application on a platform. The approach is based on Scenario-Aware Dataflow (SADF) models. In contrast to the related work, we express the complete design-space in a single formal SADF model. This allows us to have a compact and explorable state-space linked with an executable model capable of symbolically analyzing different mappings for their timing behavior. We can model different bindings for application tasks, different static-orders schedules for tasks bound in shared resources, as well as naturally capturing resource claiming/unclaiming using SADF semantics. Moreover, by using the inherent properties of dataflow graphs and the dynamic behavior of a Finite-State Machine, we can model different levels of pipelining, such as full application pipelining and interleaved pipelining of consecutive executions of the application. The size of the model is independent of the number of executions of the application. Since we are able to capture all this behavior in a single SADF model we can use available dataflow analysis, such as worst-case and best-case throughput and deadlock-freedom checking. Furthermore, since the model captures the design-space independently of the analysis technique, one can use different exploration approaches to analyze different sets of requirements. I. INTRODUCTIONIn a traditional approach to system design, the first exploration phase focuses on iterating over different design alternatives to find the best solution that satisfies a given set of requirements and constraints. For example, real-time embedded systems have to perform under strict timing guarantees, or high-performance production systems focus on maximizing resource utilization to achieve maximal throughput. However, exploring different design alternatives is highly dependent on an efficient binding and scheduling of the application in order to analyze the performance of each design. Therefore, several approaches have been proposed to model and explore different mapping options. However, current modeling approaches for the binding and scheduling are not transparent, use different models for application and platform or rely on later transformations to different models and formalisms to solve the actual state-space exploration problem.In this paper 1 we present a modeling approach based on Scenario-Aware Dataflow (SADF) that provides a single, compact and formal model of the system which reflects the complete state-space for all binding and scheduling options of an application to be mapped on a given platform. Our approach allows for the modeling of both application and platform constraints, keeping all deterministic behavior of the application within static dataflow graphs and model explicitly the different choices of scheduling and binding decisions in a Finite-State Machine. The approach uses a rich formalism capable of capturing different applications or different levels of application pipelining. The resulting model uses an underlying symbolic exec...

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Modeling resource sharing using FSM-SADF

Cited by 4 publications

References 10 publications

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Towards State-Based RT Analysis of FSM-SADFGs on MPSoCs with Shared Memory Communication

Compositional specification of functionality and timing of manufacturing systems

Modeling resource sharing using FSM-SADF

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