Modified architecture of FFT module using CSD multiplier and Dual Edge Triggered Flip Flop

Abstract

Wireless communication system increases rapidly in the digital world. As it increases need of high band width but allocation of band width in the minimum range in such that case system should be designed in the way of efficiently usage of the band width. OFDM is widely used in all wireless communication networks for modulation. In that FFT and IFFT is the main module, which is used for domain conversion. Delay in the system due to the domain conversion. By increasing the speed of the FFT and IFFT block performance can be increased for the system. Normally D Flip Flop and complex multiplier is used in the architecture. The module is modified by CSD multiplier and Dual Edge Triggered Flip Flop instead of Complex multiplier and D Flip Flop. By this modified architecture system speed and high band width utilization can be done. Modified FFT module is implemented in Vertex-4 kit using XILINX software. The RTL code is implemented in the design using Verilog code.