Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs

Jain, Abhishek Kumar; Ravishankar, Chirag; Omidian, Hossein; Kumar, Sharan; Kulkarni, Maithilee Nagesh; Tripathi, Aashish; Gaitonde, Dinesh

doi:10.1109/fccm57271.2023.00023

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Cited by 6 publications

References 34 publications

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HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory

Tareen,

Meyer,

Plessl

et al. 2024

2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory

Tareen,

Meyer,

Plessl

et al. 2024

2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

View full text Add to dashboard Cite

HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator

Yu,

Sreeram,

Agrawal

et al. 2024

2024 34th International Conference on Field-Programmable Logic and Applications (FPL)

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A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

Szafarczyk,

Nabi,

Vanderbauwhede

2023

2023 International Conference on Field Programmable Technology (ICFPT)

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Dynamically scheduled high-level synthesis (HLS) achieves a higher throughput on codes with unpredictable memory accesses compared to statically scheduled HLS. However, the increased throughput comes at the price of increased resource usage and critical path length, resulting in lower clock frequency. The decrease in clock frequency can be significant, often nullifying any throughput improvements over static scheduling. Recent work presented methods for combining static and dynamic scheduling to achieve high throughput circuits with a fast critical path for dynamic codes. However, circuits that require dynamically scheduled memory still suffer from a decreased frequency. This paper fills this gap by presenting a method for achieving dynamically scheduled memory operations in HLS with a high frequency. Dynamic scheduling of memory operations is realized with a load-store queue (LSQ). We present a novel LSQ design adapted to the nature of spatial architectures with aggressive specialization to the target code -a unique opportunity in HLS. Our LSQ design works for both on-chip and off-chip memory and is integrated with a compiler that combines dynamic and static scheduling. We show a method to speculatively allocate addresses to our LSQ, significantly increasing pipeline parallelism in codes that could not benefit from an LSQ before. In stark contrast to traditional load value speculation, our approach adds no overhead on misspeculation. On a set of ten benchmarks, we show that our approach can achieve an up to 10× speedup on average against static HLS, and an up to 4× speedup against dynamic HLS that uses an LSQ from previous work, while also using several times fewer resources and scaling to larger queues.

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Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs

Cited by 6 publications

References 34 publications

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory

HiHiSpMV: Sparse Matrix Vector Multiplication with Hierarchical Row Reductions on FPGAs with High Bandwidth Memory

HASS: Hardware-Aware Sparsity Search for Dataflow DNN Accelerator

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis

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