Monitoring and timing prediction in early analyzing and checking performance of interconnection networks at ESL

Abstract

When an advanced interconnection architecture with many routers (or switches) is designed to integrate a large number of system components into a single chip, its performance has to be analyzed or verified. This will take considerable time if no cost-effective technique is developed to deal with the complex task. In the paper, we present an early timing checking technique to verify interconnection performance at electronic system level. Experimental results show that the proposed technique has better violation detection efficiency than other ones.