MoNoC: A monitored network on chip with path adaptation mechanism

Moreno, E.; Webber, Thais; Marcon, César; Moraes, Fernando; Calazans, Ney

doi:10.1016/j.sysarc.2014.10.002

Cited by 5 publications

(4 citation statements)

References 39 publications

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“…With single frequency allocation in Figure 3a, the maximum test time out of three I/O pair was 18,546 ns (considering a normalized test frequency of 1GHz) whereas, with multiple frequencies in Figure 3b, it was 12,439 ns considering the three clock frequencies 1 2 GHz, 1 GHz and 2 GHz, which showed the reduction in test time. With single frequency allocation, assuming a normalized test frequency of 1Hz in Figure 2a, maximum test time out of three I/O pair is 12,452 s.…”

Section: Motivationmentioning

confidence: 98%

“…This value of 30% was chosen to stringent the power constraints for our experiments [9]. We have further constrained the frequency to increase by factor two for some of the cores with lower power budget and at the same time the frequency is slow down by factor 1 2 . With higher power budget cores.…”

Section: Motivationmentioning

confidence: 99%

“…The bus-based TAM was being widely used in SoC. The typical bus-based TAM architecture for SoC is having blems related to scalable global synchronous clock, communication time and performance issues [1]. To overcome these issues, NoC based SoCs are introduced.…”

Section: Introductionmentioning

confidence: 99%

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ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Parmar

Mehta

2019

JLPEA

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Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

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Section: Motivationmentioning

confidence: 98%

Section: Motivationmentioning

confidence: 99%

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ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Parmar

Mehta

2019

JLPEA

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“…WENS have been widely deployed recently to support Internet-of-things [3,4,5,6]. Bulk data dissemination is used to distribute a large data object reliably from a sink node to all network nodes in WENS, becoming an essential building module for a variety of WENS systems, e.g., remote software management [7], security patches [8], reprogramming [9,10] and video distribution [11].…”

Section: Introductionmentioning

confidence: 99%

Highly-Efficient Bulk Data Transfer for Structured Dissemination in Wireless Embedded Network Systems

Zhao

Wang

Min

et al. 2017

Journal of Systems Architecture

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Recent years have witnessed the remarkable development of wireless embedded network systems (WENS) such as cyber-physical systems and sensor networks. Reliable bulk data dissemination is an important building module in WENS, supporting various applications, e.g., remote software update, video distribution. The existing studies often construct network structures to enable time-slotted multi-hop pipelining for data dissemination. However, the adopted transmission mechanism was originally designed for structureless protocols, and thus posing significant challenges on efficient structured data dissemination. In this paper, we investigate the problem of structured bulk data dissemination. Specifically, we propose reliable out-of-order transmission and bursty encoding mechanisms to transmit packets as many as possible in each transmission slot. As a consequence, the resulting transmission protocol (ULTRA) can fully utilize each transmission slot and propagate data in the network as fast as possible. The performance results obtained from both testbed and simulation experiments demonstrate that, compared to the state-of-the-art protocols, ULTRA can greatly enhance the dissemination performance by reducing the dissemination delay by 34.8%.

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Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency

Parmar

Mehta

2017

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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MoNoC: A monitored network on chip with path adaptation mechanism

Cited by 5 publications

References 39 publications

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Highly-Efficient Bulk Data Transfer for Structured Dissemination in Wireless Embedded Network Systems

Power Aware Network on Chip Test Scheduling with Variable Test Clock Frequency

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