MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

Singh, Hartej; Lee, Ming-Hau; Lu, Guangming; Kurdahi, Fadi; Bagherzadeh, Nader; Filho, E.M.C.

doi:10.1109/12.859540

Cited by 734 publications

(447 citation statements)

References 23 publications

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“…CGRAs can be used as SIMD machines, and in fact some [10] report the result of mapping a cryptography kernel to a CGRA using a SIMD style. However, how to map loops optimally to a CGRA using a SIMD style and what are the issues are largely unexplored.…”

Section: Related Workmentioning

confidence: 99%

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

Kim

Lee

et al. 2012

Lecture Notes in Computer Science

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Abstract. Reconfigurable Architecture (RA), which provides extremely high energy efficiency for certain domains of applications, have one problem that current mapping algorithms for it do not scale well with the number of cores. One approach to this problem is using SIMD (Single Instruction Multiple Data) paradigm. However, SIMD can complicate the mapping problem by adding an additional dimension, i.e., iteration mapping, to the already inter-dependent problems of data mapping and operation mapping, and can significantly affect performance through memory bank conflicts. In this paper we introduce SIMD reconfigurable architecture, which allows for SIMD mapping at multiple levels of granularity, and investigate ways to minimize bank conflicts in a SIMD reconfigurable architecture with the related sub-problems taken into consideration. We further present data tiling and evaluate a conflict-free scheduling algorithm as a way to eliminate bank conflicts for a certain class of iteration and data mapping.

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Section: Related Workmentioning

confidence: 99%

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

Kim

Lee

et al. 2012

Lecture Notes in Computer Science

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“…MorphoSys [8] is composed of a tiny RISC main processor and an 8 × 8 ALU RCA that performs 16-bit operations in SIMD mode. A high-bandwidth memory interface consists of a frame buffer and a DMA controller that sits between the external memory and RCA.…”

Section: Related Workmentioning

confidence: 99%

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Gu-gang

Cao

Yang

et al. 2013

IEICE Trans. Inf. & Syst.

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SUMMARYOne of the largest challenges for coarse-grained reconfigurable arrays (CGRAs) is how to efficiently map applications. The key issues for mapping are (1) how to reduce the memory bandwidth, (2) how to exploit parallelism in algorithms and (3) how to achieve load balancing and take full advantage of the hardware potential. In this paper, we propose a novel parallelism scheme, called 'Hybrid partitioning', for mapping a H.264 high definition (HD) decoder onto REMUS-II, a CGRA systemon-chip (SoC). Combining good features of data partitioning and task partitioning, our methodology mainly consists of three levels from top to bottom: (1) hybrid task pipeline based on slice and macroblock (MB) level; (2) MB row-level data parallelism; (3) sub-MB level parallelism method. Further, on the sub-MB level, we propose a few mapping strategies such as hybrid variable block size motion compensation (Hybrid VBSMC) for MC, 2D-wave for intra 4 × 4, parallel processing order for deblocking. With our mapping strategies, we improved the algorithm's performance on REMUS-II. For example, with a luma 16 × 16 MB, the Hybrid VBSMC achieves 4 times greater performance than VBSMC and 2.2 times greater performance than fixed 4 × 4 partition approach. Finally, we achieve 1080p@33fps H.264 high-profile (HiP)@level 4.1 decoding when the working frequency of REMUS-II is 200 MHz. Compared with typical hardware platforms, we can achieve better performance, area, and flexibility. For example, our performance achieves approximately 175% improvement than that of a commercial CGRA processor XPP-III while only using 70% of its area.

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“…We implement a detailed performance simulator based on Morphosys [3] 2 by extending Simplescalar-3.0d. Morphosys is chosen as a basic underlying hardware because of the following reasons.…”

Section: Resultsmentioning

confidence: 99%

“…Since SM-SIMD architecture can get smaller die size and less power consumption, SM-SIMD architecture is widely used in embedded SOCs [3][4][5][6][7][8][9]. Although the details of these SOCs are not completely the same, there are some common characteristics among them in order to fit mobile computing circumstance.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, multiple-SIMD architecture instead of single SIMD unit is becoming a dominant multimedia accelerator in modern multimedia processors. At present, there are two types of multiple-SIMD architectures: one is shared memory multiple-SIMD architecture (SM-SIMD) [3][4][5][6][7][8][9] , where multiple SIMD units share a common memory (cache) on chip. The other is distributed memory multiple-SIMD architecture (DM-SIMD) [10], on which each SIMD unit has its local memory.…”

Section: Introductionmentioning

confidence: 99%

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Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture

Zhang

Bao

Zang

et al.

Languages and Compilers for Parallel Computing

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Abstract. The rapid growth of multimedia applications has been putting high pressure on the processing capability of modern processors, which leads to more and more modern multimedia processors employing parallel single instruction multiple data (SIMD) units to achieve high performance. In embedded system on chips (SOCs), shared memory multiple-SIMD architecture becomes popular because of its less power consumption and smaller chip size. In order to match the properties of some multimedia applications, there are interconnections among multiple SIMD units. In this paper, we present a novel program transformation technique to exploit parallel and pipelined computing power of modern sharedmemory multiple-SIMD architecture. This optimizing technique can greatly reduce the conflict of shared data bus and improve the performance of applications with inherent data pipeline characteristics. Experimental results show that our method provides impressive speedup. For a shared memory multiple-SIMD architecture with 8 SIMD units, this method obtains more than 3.6X speedup for the multimedia programs.

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MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

Cited by 734 publications

References 23 publications

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

Data Pipeline Optimization for Shared Memory Multiple-SIMD Architecture

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