Multi‐layer on‐chip inductor for 10–100 GHz frequency applications

Abstract

A multi-layer inductor is proposed to achieve high inductance with moderate Q-factor values. The development of integration of devices technology in radio-frequency (RF) has increased the importance of on-chip inductors. In the literature, the planar inductor, the threedimensional (3D) inductor with constant width and the 3D inductor with variable width are reported. Using the basic concept of multilayer technology in very large-scale integration (VLSI) system design and considering lambda rules, the proposed inductor is designed. The inductance of the proposed inductor is nearly 37-45% higher compared with reported inductors with a moderate quality factor. This inductor is realised using 180 nm scale technology with an area of cross-section 10 × 10 µm 2 . Results are presented using the IE3D EM field solver with the help of series RL and shunt RC lumped Pi model. Introduction:The inductor plays a key role in the design of on-chip radio-frequency (RF) requirements. For circuits such as voltage controlled oscillators and low-noise amplifiers, the value of the inductance and the Q-factor are very important in the design of spiral inductor [1]. With the trend in silicon processing technologies, there is huge improvement in RF circuits based on transistor speed and cutoff frequency. RF circuits will be more beneficial when they are designed with inductors of small size, high inductance and high quality factor. In the literature, inductors made of silicon IC process had a quality factor of 12 [2][3][4]. The Q-factor mainly depends on two main losses [5], the ohmic loss and eddy current loss. Ohmic loss is due to thin metal layers and eddy current loss is due to high substrate coupling. The substrate and metal losses in a standard silicon process lead to reducing the selfresonant frequency and quality factor of the conventional inductor [6,7]. To overcome this problem, conductors of inductor are placed in multi-layers in order to decrease negative mutual inductance by increasing the gap between conductors, which increases total inductance. There are many techniques to design inductors in existing systems. Some are the conventional CMOS inductor, others the CMOS-MEMS inductor [8,9]. The reported values of Q-factor and inductance for the existing systems are at 8 and 13 at 5.8 GHz. The inductor proposed in this Letter has an inductance of 0.173 nH and Q-factor value of 16.4 at 100 GHz. To develop cost-effective silicon systems, optimised inductor performance in terms of area at the application frequency is required.

Design of a multilayer on-chip inductor by computational electromagnetic modelling

“…The search is on for novel on-chip spiral, multilayer and 3-D inductors with large L , small area, low loss and high Q . This requires modeling the inductance characteristics of such structures accurately and efficiently for automated design [2] Integrating inductors on chip greatly increases system integrity and reduces the packaging parasitic effects. However, because of their large chip area and significant leakage of magnetic energy, on-chip inductors also affect the performance of high-frequency integrated circuits through an electromagnetic coupling [3].…”