Multi-level fault simulation of digital systems on decision diagrams

Ubar, Raimund; Raik, Jaan; Ivask, E.; Brik, Marina

doi:10.1109/delta.2002.994594

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…During the last decade, the HLDDs have been used in different fields of highlevel and hierarchical test. As the result, new promising algorithms, techniques and prototype tools have been developed, which allowed to improve the efficiency of RT level cycle based simulation [63,64], hierarchical test program automated synthesis [65,66], hierarchical fault simulation [67,68], and fault diagnosis [69].…”

Section: Overview Of High Level Dds 31 Short History Of Hldd Developmentioning

confidence: 99%

Overview about low-level and high-level decision diagrams for diagnostic modeling of digital systems

Ubar

2011

FACTA U EE

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BDDs have become the state-of-the-art data structure in VLSI CAD. In this paper, a special class of BDDs is presented called Structurally Synthesized BDDs (SSBDD). The idea of SSBDDs is to establish one-to-one mapping between the nodes of SSBDDs and signal paths in the related digital circuit. Such a mapping allowed to investigate and solve with SSBDDs a lot of test and diagnosis related problems of digital circuits, which are associated explicitly with the structure. Such problems are, for example, direct representation of faults, fault collapsing and fault masking, delay testing, hazard detection, etc. The main concept of using SSBDDs is laying on the topological view on the graphs, where each path on a SSBDD can be mapped directly to a subcircuit of the related circuit. Such a topological view allowed to generalize the knowledge and methods of test synthesis and fault analysis from the Boolean level to higher register-transfer and behavior levels of digital systems by introducing High-Level DDs (HLDD). The paper gives a short historical overview of the development of SSBDDs and HLDDs.

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Section: Overview Of High Level Dds 31 Short History Of Hldd Developmentioning

confidence: 99%

Overview about low-level and high-level decision diagrams for diagnostic modeling of digital systems

Ubar

2011

FACTA U EE

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“…The authors of this paper proposed a concept of hierarchical fault simulation [6] using a deductive algorithm on High-Level Decision Diagram (HLDD) models [7]. The method assumed that gate-level descriptions of all the modules exist and modeled faults in the circuits hierarchically at the register-transfer and logic levels.…”

Section: Introductionmentioning

confidence: 99%