Multi-State Adaptive BIT False Alarm Reduction Under Degradation Process

Abstract

Built-in tests (BITs) are widely used in mechanical systems to detect and diagnose a fault, whereas the BIT false alarms bring much trouble for precise fault diagnosis and logistics/maintenance arrangement. The false alarm phenomenon is related to the degradation over time, and the false alarm evolution process can be typically divided into three stages. This paper proposes a condition-based multistage false alarm detection and reduction method for mechanical systems. The stages are clarified according to the degradation level and the false alarm severity. The dividing boundaries of the stages are optimized using soft margin one-versus-rest support vector machine (SVM) classifiers. The associated intermediate stage is the intense period of false alarms, and the dynamic Bayesian network inference model is developed to satisfy the requirements of accurate false alarm diagnosis. To achieve the goal of false alarm suppression, the top-level BIT outputs are updated with the original BIT alarms and the identified probable states. Finally, the proposed approach is demonstrated in the application study of a milling machine and the well-round experimental results are analyzed. Index Terms-Built-in test (BIT), dynamic Bayesian network (DBN), false alarm, mechanical system, support vector machine (SVM).