Multicycle-aware At-speed Test Methodology

Abstract

Multicycle paths are commonly seen in today's high performance designs with multi-frequency clock domains. Previous methods either treat the multicycle paths as false paths and masking the transition on the paths, or slow down the clocks in order to test the multicycle paths. Both approaches would compromise the at-speed test quality. In this paper, we present an at-speed test methodology to target the faults on the multicycle paths using the same clock scheme as regular faults at the single cycle paths. The methodology takes SDC files which defines all timing exceptions and the clock frequency information and create at-speed pattern set that detects faults on both single and multicycle paths. The approach also handles all of the timing exceptions and constraints defined in SDC to prevent simulation mismatches. The experiment results on couple industrial designs demonstrate the effectiveness and efficiency of the proposed methodology to handle complex designs with large timing exception paths.