Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function

Rani, S. P. Joy Vasantha; Kanagasabapathy, P.

doi:10.1109/icscn.2007.350771

Cited by 6 publications

(6 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The results of our comparison are shown in Table 7. It can be seen that at low precision, i.e., 8-bit, design proposed in [18] fairs better as compared to RECON in terms of area and power. However, we can observe an exponential increase at higher bit precisions.…”

Section: E Recon In Af Configurationmentioning

confidence: 97%

“…Various ASIC implementations of non-linear activation functions proposed in [18], [33]- [35], employ a combinational logic-based design approach consisting of memory elements, MUX/DeMUX-trees and logic gates. All these combinational logic-based design uses quantization states to realize activation functions.…”

Section: B Related Work For Activation Functionmentioning

confidence: 99%

“…In order to carry out evaluation for our proposed design for AF computation, we also compare it with combinational logic design based AF computation as proposed in [18]. We synthesise both the designs at two technology nodes of 45nm and 180nm at different precisions to have a fair comparison.…”

Section: E Recon In Af Configurationmentioning

confidence: 99%

“…The combinational logic design-based AF proposed in [18] uses the concept of quantization states to implement nonlinear activation functions. Realization of quantization states is done through memory elements and selection using MUX tree and combinational logic gates.…”

Section: E Recon In Af Configurationmentioning

confidence: 99%

“…However, we can observe an exponential increase at higher bit precisions. Moving from 8-bit to 12-bit results in 10× increase in area and power for the design proposed in [18]. The reasons can be ascertained to the fact that for 12-bit precision, number of quantization states is equal to 2 12 = 4096 which leads to an exponential increase in the memory elements required.…”

Section: E Recon In Af Configurationmentioning

confidence: 99%

See 4 more Smart Citations

RECON: Resource-Efficient CORDIC-Based Neuron Architecture

Raut

Rai

Vishvakarma

et al. 2021

IEEE Open J. Circuits Syst.

View full text Add to dashboard Cite

Contemporary hardware implementations of artificial neural networks face the burden of excess area requirement due to resource-intensive elements such as multiplier and non-linear activation functions. The present work addresses this challenge by proposing a resource-efficient Coordinate Rotation Digital Computer (CORDIC)-based neuron architecture (RECON) which can be configured to compute both multiply-accumulate (MAC) and non-linear activation function (AF) operations. The CORDIC-based architecture uses linear and trigonometric relationships to realize MAC and AF operations respectively. The proposed design is synthesized and verified at 45nm technology using Cadence Virtuoso for all physical parameters. Implementation of the signed fixed-point 8-bit MAC using our design, shows 60% less area, latency, and power product (ALP) and shows improvement by 38% in area, 27% in power dissipation, and 15% in latency with respect to the state-of-the-art MAC design. Further, Monte-Carlo simulations for process-variations and device-mismatch are performed for both the proposed model and the state-of-the-art to evaluate expectations of functions of randomness in dynamic power variation. The dynamic power variation for our design shows that worst-case mean is 189.73μW which is 63% of the state-of-the-art. INDEX TERMS AF, CORDIC, configurable architecture, MAC, neural network.

show abstract

Section: E Recon In Af Configurationmentioning

confidence: 97%