Multilayer planarization of polymer dielectrics

Abstract

Polymers are widely used in the microelectronics industry as thin-film interlevel dielectrics layers between metal lines, as passivation layers on semiconductor devices and in various packaging applications. As multiple layers of polymer and patterned metal are constructed, the ability of these polymers to planarize topographical features becomes increasingly important. In this study, the degree of planarization (DOP) for five commercially available polymers has been examined for three different structural configurations with the intent of simulating practical applications. Specifically, this study investigates single layer planarization, multiple coat planarization, and planarization of metal lines patterned on a polymer base. This study also examines the effects of orientation of the metal structure to polymer flow during spin casting and location on the wafer. The polymers were selected to investigate different polymer chemistries frequently used in the microelectronics industry. The underlying structures were fabricated using standard photolithography and electroplating techniques. Feature dimensions include 25-200 m line spacings and widths with the polymer overcoat thickness being twice the height of the underlying structures.

Planarization of CMOS ROIC dies for uncooled detectors

“…And two layers of BCB with spin speed at 5000 rpm and 3000 rpm can further improve the planarization level by reducing the surface topology to about 800 and 600 Å , respectively. The final surface roughness of 600-800 Å is in substantial agreement with the reported value of 600 Å and the measured DOP of 93% and 97% for one and two layers of BCB are also well coinciding with the reported values of 90% and 97% [4,10].…”

“…Punit Chiniwalla has successfully planarized the surface topology of an experimental structure from 2 lm to about 800 Å using spin coating method [4]. Hocheol Lee has also reduced the surface roughness of a CMOS die for integration with metal mirror arrays from 0.9 lm to less than 250 Å using Chemical Mechanical Polishing (CMP) technology [5].…”

Adding functionality to microchips by wafer post-processing

“…Non-planar substrates complicate spin coating, the step-coverage and patterning of deposited layers, and may conflict with the limited depth-of-focus of lithography. Chemical-mechanical polishing is a convenient planarization technique at this stage [38]; also, one may apply planarizing thin films [39]. For optical functionality such as in LCoS systems (see Section 5), flatness is even more important, and additional measures are taken [40].…”

Electron beam enhanced multilayering and planarization in preimidized polyimides

“…In a previous study [4], it was found that the planarization of a preimidized polyimide (Ultradel 7501) is significantly compromised by solvent diffusion from one layer of the polyimide to the other. The degree of planarization (DOP), defined by equation (1) and Fig.…”