Multilevel full-chip gridless routing considering optical proximity correction

Abstract

To handle modern routing with nanometer effects, we need to consider designs of variable wire widths and spacings, for which gridless routers are desirable due to their great flexibility. The gridless routing is much more difficult than the grid-based one because the solution space of gridless routing is significantly larger than that of grid-based one. In this paper, we present the first multilevel, full-chip gridless detailed router. The router integrates global routing, detailed routing, and congestion estimation together at each level of the multilevel routing. It can handle non-uniform wire widths and consider routability and optical proximity correction (OPC). Experimental results show that our approach obtains significantly better routing solutions than previous works. For example, for a set of 11 commonly used benchmark circuits, our approach achieves 100% routing completion for all circuits while the famous state-of-the-art three-level routing and multilevel routing (multilevel global routing + flat detailed routing) cannot complete routing for any of the circuits. Besides, experimental results show that our multilevel gridless router can handle non-uniform wire widths efficiently and effectively (still maintain 100% routing completion for all circuits). In particular, our OPC-aware multilevel gridless router archives an average reduction of 11.3% pattern features and still maintains 100% routability for the 11 benchmark circuits.

A novel framework for multilevel full-chip gridless routing

“…Therefore, as the designs grow, more levels of routing are needed [10]. Recently, we proposed an OPC-aware multilevel gridless router based on the Λ-shaped framework [4], which integrates gridless global and detailed routing at each level. The router can handle non-uniform wire widths and reduce OPC pattern feature requirements.…”

“…[3,22], [4], [8,9,10], [12,13,14] by top-down uncoarsening, VMF adopts the two-stage technique of top-down uncoarsening followed by bottom-up coarsening. See Figure 1(b) for an illustration of VMF.…”

“…• The previous works [3,4,22] perform greedy global routing, which determines the global path of the current net without considering the routing resource of succeeding nets. In contrast, VMGR employs a congestion map to guide the global routing at all stage.…”

“…Table I compares the existing multilevel routing frameworks among [3,22], [4], [8,9,10], [12,13,14], and VMF.…”

“…To cope with the increasing complexity, the multilevel framework is proposed to solve the routing problems (e.g., MRS [8], MARS [9,10], MR [3,22], CMR [12,14], MGR [4], XMR [15]) as well as graph/circuit partitioning (e.g., Chaco [11], ML [1], hMETIS [19], HPM [7]), floorplanning (e.g., MB*-tree [21], MLGFA [16]), and placement (e.g., mPL [2] and APlace [17,18]). All of the existing multilevel frameworks adopt a two-stage technique, bottom-up coarsening followed by top-down uncoarsening, which is known as the "Λ-shaped" framework.…”