Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing

Abstract

With the reduced-pin-count test (RPCT) being adopted for multi-core systems-on-chip (SoCs) that usually support test compression as well, test speed is reduced due to the narrower input bandwidth. In this work, we propose an idea to combine multi-valued logic (MVL) test application with RPCT technology, which increases the data rate of test channels to avoid compromising test speed for the interface. The hardware modifications for the tester and device under test (DUT) are proposed with the corresponding test flow. Simulation result shows that the test speed is increased by four times with 4-bit MVL test channel. An actual ATE experiment verifies that only 61,757 cycles are used to complete a RPCT with MVL test application, compared to 247,020 cycles for an RPCT only scenario.