NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level

Wilson, Ellis; Donofrio, David; Shalf, John; Kandemir, Mahmut

doi:10.1109/msst.2012.6232389

Cited by 39 publications

(16 citation statements)

References 7 publications

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“…Bucy et al [2009] developed a DiskSim-based simulator to estimate the energy consumption of HDDs for a given workload. Jung et al [2012] developed NANDFlashSim for NAND flash devices.…”

Section: Related Workmentioning

confidence: 99%

Design Tradeoffs of SSDs

et al. 2015

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In this work, we studied the energy consumption characteristics of various SSD design parameters. We developed an accurate energy consumption model for SSDs that computes aggregate, as well as componentspecific, energy consumption of SSDs in sub-msec time scale. In our study, we used five different FTLs (page mapping, DFTL, block mapping, and two different hybrid mappings) and four different channel configurations (two, four, eight, and 16 channels) under seven different workloads (from large-scale enterprise systems to small-scale desktop applications) in a combinatorial manner. For each combination of the aforementioned parameters, we examined the energy consumption for individual hardware components of an SSD (microcontroller, DRAM, NAND flash, and host interface). The following are some of our findings. First, DFTL is the most energy-efficient address-mapping scheme among the five FTLs we tested due to its good write amplification and small DRAM footprint. Second, a significant fraction of energy is being consumed by idle flash chips waiting for the completion of NAND operations in the other channels. FTL should be designed to fully exploit the internal parallelism so that energy consumption by idle chips is minimized. Third, as a means to increase the internal parallelism, increasing way parallelism (the number of flash chips in a channel) is more effective than increasing channel parallelism in terms of peak energy consumption, performance, and hardware complexity. Fourth, in designing high-performance and energy-efficient SSDs, channel switching delay, way switching delay, and page write latency need to be incorporated in an integrated manner to determine the optimal configuration of internal parallelism.

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“…Bucy et al [2009] developed a DiskSim-based simulator to estimate the energy consumption of HDDs for a given workload. Jung et al [2012] developed NANDFlashSim for NAND flash devices.…”

Section: Related Workmentioning

confidence: 99%

Design Tradeoffs of SSDs

et al. 2015

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“…All of our experiments utilize our NANDFlashSim simulation framework, described in detail in [14], which enables highly accurate timing models for the NVM types we examine. Further, we utilize queuing optimizations within NANDFlashSim as discussed in [15], to refine our findings for future NVM devices.…”

Section: Experimental Configurationmentioning

confidence: 99%

Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory

Wilson

Choi

Shalf

et al. 2014

Scientific Programming

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Abstract. Drawing parallels to the rise of general purpose graphical processing units (GPGPUs) as accelerators for specific high-performance computing (HPC) workloads, there is a rise in the use of non-volatile memory (NVM) as accelerators for I/O-intensive scientific applications. However, existing works have explored use of NVM within dedicated I/O nodes, which are distant from the compute nodes that actually need such acceleration. As NVM bandwidth begins to out-pace point-to-point network capacity, we argue for the need to break from the archetype of completely separated storage.Therefore, in this work we investigate co-location of NVM and compute by varying I/O interfaces, file systems, types of NVM, and both current and future SSD architectures, uncovering numerous bottlenecks implicit in these various levels in the I/O stack. We present novel hardware and software solutions, including the new Unified File System (UFS), to enable fuller utilization of the new compute-local NVM storage. Our experimental evaluation, which employs a real-world Out-of-Core (OoC) HPC application, demonstrates throughput increases in excess of an order of magnitude over current approaches.

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“…FlashPower uses measurements from actual chips and combines it with a detailed parameterized analytical model for NAND flash memories. NANDFlashSim is a microarchitecture level tool that simulates only the performance characteristics of NAND flash chips [30]. NANDFlashSim can be used on top of circuitlevel analytical modeling tools like FlashPower to provide a flash simulation infrastructure that models both energy and performance.…”

Section: Design Space Exploration Using Flashpowermentioning

confidence: 99%

Modeling Power Consumption of NAND Flash Memories Using FlashPower

Mohan

Bunker

Grupp

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Flash is the most popular solid-state memory technology used today. A range of consumer electronics products, such as cell-phones and music players, use flash memory for storage and flash memory is increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and servers. There is a rich microarchitectural design space for flash memory and there are several architectural options for incorporating flash into the memory hierarchy. Exploring this design space requires detailed insights into the power characteristics of flash memory. In this paper, we present FlashPower, a detailed power model for the two most popular variants of NAND flash, namely, the Single-Level Cell (SLC) and 2-bit Multi-Level Cell (MLC) based flash memory chips. FlashPower is built on top of CACTI, a widely used tool in the architecture community for studying various memory organizations. FlashPower takes several parameters like the device technology, microarchitectural layout, bias voltages and workload parameters as input to estimate the power consumption of a flash chip during its various operating modes. We validate FlashPower against chip power measurements from several different manufacturers and show that our results are comparable to the actual chip measurements. We illustrate the versatility of the tool in a design space exploration of power optimal flash memory array configurations.

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NANDFlashSim: Intrinsic latency variation aware NAND flash memory system modeling and simulation at microarchitecture level

Cited by 39 publications

References 7 publications

Design Tradeoffs of SSDs

Design Tradeoffs of SSDs

Exploring the Future of Out-of-Core Computing with Compute-Local Non-Volatile Memory

Modeling Power Consumption of NAND Flash Memories Using FlashPower

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