Nanopower Integrated Gaussian Mixture Model Classifier for Epileptic Seizure Prediction

Abstract

This paper presents a new analog front-end classification system that serves as a wake-up engine for digital back-ends, targeting embedded devices for epileptic seizure prediction. Predicting epileptic seizures is of major importance for the patient’s quality of life as they can lead to paralyzation or even prove fatal. Existing solutions rely on power hungry embedded digital inference engines that typically consume several µW or even mW. To increase the embedded device’s autonomy, a new approach is presented combining an analog feature extractor with an analog Gaussian mixture model-based binary classifier. The proposed classification system provides an initial, power-efficient prediction with high sensitivity to switch on the digital engine for the accurate evaluation. The classifier’s circuit is chip-area efficient, operating with minimal power consumption (180 nW) at low supply voltage (0.6 V), allowing long-term continuous operation. Based on a real-world dataset, the proposed system achieves 100% sensitivity to guarantee that all seizures are predicted and good specificity (69%), resulting in significant power reduction of the digital engine and therefore the total system. The proposed classifier was designed and simulated in a TSMC 90 nm CMOS process, using the Cadence IC suite.

General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers

“…The volume of input dimensions is contingent on the multidimensional Gaussian function circuit. While there exist various circuits that yield PDFs, extant literature confines their application to dimensions of a modest scale, typically less than 16 [20,65].…”

“…A broad spectrum of bump circuits has been developed for numerous applications [20]. However, for the purposes of this research, a modified version of the bump circuit (aspect ratio equal to 7) [65], as shown in Figure 3, has been employed to enhance the quality and resilience of the resulting Gaussian curve. Specifically, the adjusted circuit employs a symmetric current correlator (comprising transistors M p1 -M p6 in Figure 3) with a ratio of 2 instead of the non-symmetric version utilized in [41].…”

“…A resolution to this challenge arises through the utilization of a cascaded WTA circuit, as depicted in Figure 6. The devised configuration integrates three WTA circuits interconnected in a cascaded manner [65]. The one-dimensional decision boundaries of the conventional Lazzaro WTA circuit and the proposed cascaded version are visualized in Figure 7.…”

A Low-Power Analog Integrated Euclidean Distance Radial Basis Function Classifier

“…One approach to tackle this challenge involves implementing a cascaded WTA circuit, illustrated in Figure 6. This devised setup integrates three WTA circuits interconnected in a cascaded manner [83]. Figure 7 provides visual representations of the one-dimensional decision boundaries for both the traditional Lazzaro WTA circuit and the proposed cascaded version.…”

Highly parallel and ultra-low-power probabilistic reasoning with programmable gaussian-like memory transistors

“…Given the importance and versatility of GMM, previous studies have investigated GMM computation hardware intensively utilizing dynamic random-access memory (DRAM) 25 , field-programmable gate array (FPGA) 26 – 28 , or analog circuits. However, usually a large number of transistors was required, which inevitably resulted in a high level of complexity 29 . Consequently, without innovative technologies that can dramatically reduce resource demands when dealing with high-dimensional complex distribution functions like GMMs, the advantages of probabilistic inference procedures remain out of reach for numerous applications.…”