Network-on-chips on 3-D ICs: Past, present, and future

Kumar, Mayank; Murali, Srinivasan; Kamakoti, V.

doi:10.4103/0256-4602.101313

Cited by 8 publications

(4 citation statements)

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“…The purpose of the Via is to connect the layers of the IC vertically. Network-on-Chip (NoC) circuitry is made above the silicon substrate [19]. This is known as 3D monolithic NoC.…”

Section: Three Dimensional (3d) Nocmentioning

confidence: 99%

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Balamurugan¹,

Umamaheswaran

Mamo³

et al. 2022

J. Phys. Commun.

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A few decades ago, communication inside the chip is done by transferring signals between the cores. This conventional method is not worthy because of the increase in latency and power consumption. To rectify this issue Network-on-Chip (NoC) technology has emerged. NoC technology is invented to transfer data packets instead of signals. Machine Learning NoC (M/LNoC) is a very fast-growing technology in today’s Integrated Circuit world for the communication between Intellectual property (IP) cores. The machine learning algorithms are used in the existing and emerging novel NoCs. In this paper, various evolving NoC technologies to decrease the transfer latency, power consumption of the IC is addressed for the implementation of the machine learning algorithm. The NoCs working with machine learning algorithms are called M/L NoC. We also provided the security issues to be focused- on in the M/L NoC. Also, we have provided the available NoC tools for the NoC researchers.

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“…The purpose of the Via is to connect the layers of the IC vertically. Network-on-Chip (NoC) circuitry is made above the silicon substrate [19]. This is known as 3D monolithic NoC.…”

Section: Three Dimensional (3d) Nocmentioning

confidence: 99%

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Balamurugan¹,

Umamaheswaran

Mamo³

et al. 2022

J. Phys. Commun.

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“…Processes in chemical engineering require contactors that can provide a higher interfacial area and mass transfer efficiency [2]. Newly developed advanced swirling contactors in mass transfer process intensification include Swirltube, ConSep Sulzer [3][4][5][6], Ultra-Frac [7,8], CoFlo [9,10], UOP SimulFlow [11], and vortex trays [12]. The rotor-stator spinning disc under the rotation of a motor can also enhance mass transfer in swirling flows [13,14].…”

Section: Introductionmentioning

confidence: 99%

Bubble Interfacial Area in a Swirling Contactor: Experiments and Computational Fluid Dynamics Simulations

Xu,

Gong,

Wang

et al. 2023

Chem Eng & Technol

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The bubble size, gas holdup, and interfacial area in a swirling contactor were investigated through experiments and simulations. The interfacial area was obtained for liquids and gases with Reynolds numbers Rel and Reg, respectively. The contactor was divided into twelve subregions. Rel was negatively related to bubble size, gas holdup, and interfacial area, whereas Reg was positively associated. The maximum bubble interfacial area for the entire swirling contactor was 196.3 m−1 with a gas‐liquid ratio of 0.022. There is a trade‐off between centrifugal acceleration and bubble size for interfacial area.

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“…5 The coupled on-chip interconnects face thermal noise due to resistive heating, 6 which limits the current density and causes the breakdown. [14][15][16][17][18] With the help of cross talk cancellation techniques like cross talk waveform, 19 twisted differential pair lines 20 are used to diminish the cross talk noise. 7 Coupling causes other important noise in interconnects, which is popularly known as cross talk noise.…”

Section: Introductionmentioning

confidence: 99%

“…Due to that, victim line experiences noise in the form of peaks of overshoot and undershoot. [14][15][16][17][18] With the help of cross talk cancellation techniques like cross talk waveform, 19 twisted differential pair lines 20 are used to diminish the cross talk noise.…”

Section: Introductionmentioning

confidence: 99%

Modeling of CMS‐based nonuniform interconnects using FDTD technique

Kolanti¹,

Sulochana

Vobulapuram³

et al. 2018

Circuit Theory & Apps

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This paper presents the finite-difference time-domain model of nonuniform interconnects including skin effect losses based on the current mode signaling (CMS). For accurate analysis, the nonlinear CMOS inverter is used as a driver for coupled nonuniform interconnects. These effects are incorporated in the proposed model using the modified alpha power law model. Additionally, high-frequency losses are incorporated in the proposed model that further improves the accuracy. Using the proposed model, the performance of nonuniform interconnects is investigated using the CMS scheme. Timedomain analysis model is derived from CMS nonuniform interconnects using finite-difference time-domain technique. Both inductive and capacitive couplings have been considered to incorporate coupling effects in interconnects. The efficiency of CMS interconnects is evaluated by comparing with conventional voltage mode signaling interconnects. The propagation delays and dynamic and functional cross talk effects at the far end of the coupled nonuniform interconnect are analyzed at the 32-nm technology node. The proposed model results are validated using the standard HSPICE simulations. KEYWORDS CMS, cross talk and propagation delay, FDTD, nonuniform interconnects, skin effects | INTRODUCTIONThe sustained technology scaling in very-large-scale integration leads to high complexity in integrated circuits. Due to scaling of technology, interconnect delays are more dominant than the gate delays. Billions of transistors are fabricated in a single chip causing high density and reduction in dimensions of the on-chip components. 1 As the global interconnects have increased lengths, delay due to parasitic components like resistor (R), capacitor (C), inductance (L), and conductance (G) are more that dominates other scaled device delays. The major source of delay and power dissipation is interconnects in miniaturized devices. These interconnects are not always uniform; they are mostly nonuniform in nature due to their complexity and particular design specifications at corners and edges of interconnect.The demand for the high-speed devices increases with the scaling of the technology; as a result, the frequency dispersion losses and noise takes place with high operating frequencies. 2,3 Due to the intersymbol interference problem in the received signal, the bit error rate increases eventually. Equalization techniques are used to diminish this nonideal effect. Different procedures, to be specific decision feedback equalization, linear equalization, pre-emphasis, deemphasis, and adaptive equalization, have been accounted for equalization techniques in interconnects. 4 The noise in

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Network-on-chips on 3-D ICs: Past, present, and future

Cited by 8 publications

References 0 publications

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Roadmap for machine learning based network-on-chip (M/L NoC) technology and its analysis for researchers

Bubble Interfacial Area in a Swirling Contactor: Experiments and Computational Fluid Dynamics Simulations

Modeling of CMS‐based nonuniform interconnects using FDTD technique

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