New architecture for cost-efficient high-performance multiple-bank RDRAM

Abstract

This DRAM realizes multiple-bank performance with small area overhead by sharing data transmission circuitry among all banks, and minimizes the time and the cost required to produce cut-down products. To enhance cost-efficiency, 2 page sizes are offered in one chip, ensuring suitability for widespread use: 1kB for low-end computers requiring low power consumption and 2kB for high-end workstations. This 288Mb RDRAM, whose architecture is shown in Figure 24.5.1a (architecture 1-A), contains four 72Mb quadrants, in the center of which row decoders (XDECs) are located horizontally. Column decoders (YDECs) are at the edge of each quadrant near the chip center. For the 2x16 split dependent bank, bank0 through bank15 and bank16 through bank31 function the same as the dependent bank. Bank15 and bank16 are, however, independent of each other. The same bank resides in 2 quadrants positioned diagonally. Both left-and right-hand halves (36Mb units) of each quadrant contain 16 banks which are arranged as 16 vertical strips. In each unit, sense amplifiers (SAs) are shared between adjacent strips. 34 global bank-select-lines (GBSLs) corresponding to the vertical rows of SAs and 36 Main DQ lines (MDQs) run horizontally over the array in half of each quadrant divided by XDECs along with column-select-lines (CSLs). MDQs are connected to the second sense amplifiers (SSAs) placed vertically at the chip center and shared between the left-and right-hand halves of the chip. Beside the SSAs, the shift registers (SRs) for 8 to 1 parallel-serial conversion are arranged vertically and transfer 144b to 18 I/O pads every column access.