New High-Speed Multioutput Carry Look-Ahead Adders

Design of adder is the most focused area in VLSI systems. In this paper, multi-output domino Manchester carry chain with carry-skip capability is proposed. In the proposed design, even and odd carries are computed independently by two parallel carry chains. Carry-skip capability is applied to the odd carry chain which reduces the worst case critical path delay. The circuits are designed and simulated using Cadence Virtuoso tool with CMOS 180nm TSMC technology and IBM 130nm technology in LT SPICE IV. The proposed 64-bit Double chain Manchester Carry chain with carry-skip Adder shows a delay reduction of 52% compared to the Double chain Manchester Carry chain. The proposed Double chain Manchester carry chain with Carry-skip logic allows the elimination of intermediate buffers, thus retaining its area. Keywords-Carry Look-ahead Adder (CLA), Manchester Carry Chain (MCC), multi-output Domino, Carry-skip logic.

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“…For the computation of sum b implementation of XOR functio implementation is depicted in F logic is used for the impleme MUX gate [12].…”

Section: This Can Be Rewritten In Terms Omentioning

confidence: 99%

High speed Manchester Carry chain with carry-skip capability

Asha

Senthilkumar

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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“…However, propagation delay obtained using RCA in long carry chains in quite high for which it became quite impractical to use RCA in high performance devices [22][23]. In order to solve the carry propagation delay in long carry chains, several Parallel-Prefix Adder topologies have been developed [24]. CLA adder is one of the PPA topologies which reduces carry propagation delay by using a complex circuitry using carry-propagate and carry-generate terms [25].…”

Section: Introductionmentioning

confidence: 99%

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Hasan¹,

Islam²,

Ahmed³

2019

CSSP

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Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.

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“…The largely accepted high speed adder is look ahead adder, skip adder, conditional sum adder, carry skip adder etc. The high speed adder with CLA (Carry Look Ahead) are extremely used but it has one limitation that it requires large number of transistors its design [1][2].…”

Section: Introductionmentioning

confidence: 99%

A high speed low power adder in dynamic logic base on transmission gate

Jain¹,

Gour²,

Shrman³

2015

2015 International Conference on Circuits, Power and Computing Technologies [ICCPCT-2015]

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Speed of operation depends on the longest critical paths in the multi-bit adders and also the MOSFET transistor gain which in turn depends on transistor size. The power consumption in MOSFET is depends on the switching frequency, sub threshold leakage and switching time. In this paper, author proposed the speed and area efficient transistor base adder using static CMOS pass transistor logic, and shortened the longest critical path to decrease the total critical path delay. The design simulation on microwind layout tool calculates the worst-case delay in nanosecond and total power consumption in microwatt range.

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New High-Speed Multioutput Carry Look-Ahead Adders

Cited by 31 publications

References 13 publications

High speed Manchester Carry chain with carry-skip capability

High speed Manchester Carry chain with carry-skip capability

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

A high speed low power adder in dynamic logic base on transmission gate

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