New IR detectors with small pixel pitch and high operating temperature

Billon-Lanfrey, David; Trinolet, Philippe; Pistone, Frédéric; Rubaldo, L.; Huet, Hubert

doi:10.1117/12.870945

Cited by 3 publications

(3 citation statements)

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“…As infrared systems become increasingly compact, maintaining consistent system performance has emerged as a critical objective. One of the primary strategies to achieve this is to decrease the pixel pitch of the infrared detector while simultaneously enhancing performance through technological advancements [ 3 , 4 , 5 , 6 ].…”

Section: Introductionmentioning

confidence: 99%

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

Hu,

Yao,

Chen

et al. 2024

Sensors

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This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital).

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Section: Introductionmentioning

confidence: 99%

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

Hu,

Yao,

Chen

et al. 2024

Sensors

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“…Nowadays, the trend of HgCdTe infrared focal plane technology development is to raise the operating temperature of HgCdTe infrared detectors [2][3] , and to reduce the power consumption of detectors and shorten the start-up time of cooler by manufacturing high operating temperature (HOT) devices, and then obtain cooled infrared focal plane detector with smaller volume and longer service life [4] . For HgCdTe HOT devices, developed countries in Europe and the United States are already in a leading position, including Sofradir in France [5][6] , AIM in Germany [7] , Selex in the United Kingdom [8] , DRS [9] and Teledyne [10] in the United States, which have made in-depth research and important research results in this direction, and launched corresponding HOT detectors. Compared with cooled infrared detectors that work at low temperatures, HOT devices have great advantages in size, mass, and volume.…”

Section: Introductionmentioning

confidence: 99%

A study of HgCdTe HOT MW infrared detector

Tan¹,

Li²,

Yan³

et al. 2023

Earth and Space: From Infrared to Terahertz (ESIT 2022)

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In this paper, we report the mid-wavelength HgCdTe HOT (High Operating Temperature) detector with 640×512 array and center distance of 15μm by JueXin Microelectronics Co., Ltd. The detector can work steadily when the focal plane array temperature is 140K. We grew up the CdZnTe substrates by vertical Bridgman technique and HgCdTe materials by liquid phase epitaxy process, then the planar n+-on-p diodes were formed by boron ion implantation. Through the optimization of material growth and device fabrication process, the dark current of the device is reduced. At 140K, the cut-off wavelength of the device is 4.7μm, the dark current density reaches 3×10 -7 A/cm 2 , and the dark current density of the device is close to that of P-on-N (rule 07). At the focal plane operating temperature of 140K, the operability of the detector can reach more than 99.5%, the NETD is less than 13mK, and the RFPN is less than 0.6mV (close to temporal noise). At the same low temperature, when the operating temperature of the device changes from 80K to 140K, the power consumption of the detector module is reduced by 37% and the cooling time is shortened by 36%.

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“…The trend in IR imaging technology is to reduce the pixel size, increase the resolution and lower the cost of the system while improving detector performance [1] .The latest development of IR system is more and more compact keeping constant system performances. One of the best approaches is to reduce the pixel pitch of the IR detector while new technology improvements are carried out to improve the detector performance [2] . In order to match the system requirements, on chip high performance ultra-low power analog to digital converter (ADC) have been develops.…”

Section: Introductionmentioning

confidence: 99%

A low-power two-step ADC for infrared FPA digital readout circuit

Hu,

Yao,

Chen

et al. 2023

Third International Computing Imaging Conference (CITA 2023)

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This paper presents a 14-bit column-parallel two-step compact hybrid ADC for low-power digital IRFPA application, with the area and speed performances compromise. The proposed two-step ADC works in two phases: in the first phase, A 7-bit SAR ADC performs the coarse quantization; in the second phase, a 7-bit SS ADC further performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, and the main clock of fine SS ADC can be reduced to 50MHz at the sampling rate of 238 kS/s. More importantly, by sharing analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are reduced consequently. The proposed two-step ADC is designed in 0.18 μm standard CMOS process. The simulation results show that the proposed two-step ADC has a differential nonlinearity of −0.87/+0.43 LSB and an integral nonlinearity of −0.86/+0.71 LSB. The layout of the proposed ADC can be implemented in the pixel pitch less than 10 μm. The conversion time is 4.2 μs, and the power consumption of each column ADC is only 65 μW with a 3.3V power supply. The simulation results indicate the proposed two-step ADC is suitable for low-power digital readout circuits in the small pixel pitch IRFPA.

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New IR detectors with small pixel pitch and high operating temperature

Cited by 3 publications

References 0 publications

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

A 14-Bit Hybrid Analog-to-Digital Converter for Infrared Focal Plane Array Digital Readout Integrated Circuit

A study of HgCdTe HOT MW infrared detector

A low-power two-step ADC for infrared FPA digital readout circuit

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